Thermal-Safe Schedule Generation for System-on-Chip Testing

2016 ◽  
Author(s):  
Rajit Karmakar ◽  
Santanu Chattopadhyay
Keyword(s):  
System On Chip ◽  
Chip Testing ◽  
On Chip

Hybrid BIST energy minimisation technique for system-on-chip testing

2006 ◽  
Vol 153 (4) ◽  
pp. 208 ◽  
Author(s):  
G. Jervan ◽  
Z. Peng ◽  
T. Shchenova ◽  
R. Ubar
Keyword(s):  
System On Chip ◽  
Energy Minimisation ◽  
Chip Testing ◽  
On Chip

VLSI AND SYSTEM-ON-CHIP REDUNDANT COMPONENTS SYNTHESIS

2018 ◽  
pp. 33-39
Author(s):  
V. V. Rozanov ◽  
E. A. Suvorova
Keyword(s):  
Fault Tolerance ◽  
Integrated Circuit ◽  
System On Chip ◽  
Point Of View ◽  
Manufacturing Defects ◽  
Asic Design ◽  
Hardware Description ◽  
Early Design Stages ◽  
Chip Testing ◽  
On Chip

Redundancy - mostly used method to increase fault tolerance of the system. Fault tolerance in modern embedded systems is important feature due to accelerating aging and manufacturing defects, which diagnosis during the chip testing at fabric is impossible. In addition, different ways of system using may need different degree of fault tolerance. From Application Specified Integrated Circuit (ASIC) design point of view redundancy means area and power increasing. On early design stages, it is necessary to see the correlation between the components hardware description and its synthesized equivalent. The article considers several variants of synthesized redundant components that show the effect on area and power regarding to their architecture. The main goal of presented research is to describe RTL and Synthesis correlation.

On System-on-Chip Testing Using Hybrid Test Vector Compression

2014 ◽  
Vol 63 (11) ◽  
pp. 2611-2619 ◽  
Author(s):  
Satyendra N. Biswas ◽  
Sunil R. Das ◽  
Emil M. Petriu
Keyword(s):  
System On Chip ◽  
Test Vector ◽  
Hybrid Test ◽  
Chip Testing ◽  
On Chip ◽  
Test Vector Compression
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