FinFET Logic Circuit Optimization with Different FinFET Styles: Lower Power Possible at Higher Supply Voltage

2014 ◽  
Author(s):  
Sourindra Chaudhuri ◽  
Niraj K. Jha
Keyword(s):  
Supply Voltage ◽  
Logic Circuit ◽  
Circuit Optimization ◽  
Lower Power

scholarly journals Design of quaternary logic systems and circuits

2005 ◽  
Vol 18 (1) ◽  
pp. 45-56 ◽  
Author(s):  
Dusanka Bundalo ◽  
Zlatko Bundalo ◽  
Branimir Ðordjevic
Keyword(s):  
Circuit Simulation ◽  
Design Procedure ◽  
Optimization Methods ◽  
Logic Circuits ◽  
Logic Circuit ◽  
Combinational Logic ◽  
Circuit Optimization ◽  
Quaternary Logic ◽  
Operation Conditions ◽  
Logic Systems

The principles and possibilities of design of fully quaternary multiple valued combinational logic systems and circuits are described and proposed in the paper. Different ways of design of fully quaternary combinational logic systems and circuits are considered and described first. Then algorithm for automated computerized design of such systems and circuits is considered and proposed. The algorithm gives possibility for synthesis and optimization of quaternary logic systems and circuits. It is applied on design of CMOS quaternary multiple valued logic systems and circuits. The algorithm includes the most important aspects of design of quaternary logic circuits: logic circuit scheme synthesis and logic circuit optimization. Methods for synthesis of quaternary CMOS combinational logic circuits are proposed and described. Also, method for optimization of CMOS quaternary logic circuits, according to operation conditions and needed characteristics, is proposed and described. Design procedure is realized by personal computer using PSPICE for circuit simulation. Computer PSPICE simulation results confirming described methods and conclusions are given in the paper.

Analog Integrated Circuit Optimization

2020 ◽  
pp. 95-130
Author(s):  
Houda Daoud ◽  
Dalila Laouej ◽  
Jihene Mallek ◽  
Mourad Loulou
Keyword(s):  
Integrated Circuit ◽  
Supply Voltage ◽  
Pso Algorithm ◽  
Circuit Optimization ◽  
Ultra Low Power ◽  
Fully Differential ◽  
Transconductance Amplifier ◽  
Threshold Voltages ◽  
Dc Gain ◽  
Low Threshold

This chapter presents a novel telescopic operational transconductance amplifier (OTA) using the bulk-driven MOS technique. This circuit is optimized for ultra-low power applications such as biomedical devices. The proposed the bulk-driven fully differential telescopic OTA with very low threshold voltages is designed under ±0.9V supply voltage. Thanks to the particle swarm optimization (PSO) algorithm, the circuit achieves high performances. The OTA simulation results present a DC gain of 63.6dB, a GBW of 2.8MHz, a phase margin (PM) of 55.8degrees and an input referred noise of 265.3nV/√Hz for a low bias current of 52nA.

Design of the Approved Low Power Energy Recovery Logic Circuit

2013 ◽  
Vol 662 ◽  
pp. 851-855
Author(s):  
Jian Ying Shi ◽  
Hui Ya Li ◽  
Yan Bin Xu
Keyword(s):  
Power Consumption ◽  
Low Power ◽  
Energy Recovery ◽  
Logic Circuits ◽  
Logic Circuit ◽  
Lower Power ◽  
Transmission Gate ◽  
Bootstrap Technique

An approved energy recovery logic circuit (AERL) was designed in this paper. In order to further reduce the power consumption of energy recovery logic circuits, the NMOS transmission gate and NMOS bootstrap technique ware used. The characteristics of the AERL circuit ware simulated using 0.5 micrometer BSIM3V3 spice models in HSPICE. The results show that the AERL circuit has much lower power consumption compared with PT-BCRL, BERL, ECRL and 2N2N-2P logic.

A Novel Current-Controlled Oscillator-Based Low-Supply-Voltage Microbolometer Readout Architecture

2020 ◽  
Vol 29 (10) ◽  
pp. 2050169
Author(s):  
Mehmet Ali Gülden ◽  
Ertan Zencir ◽  
Enver Çavuş
Keyword(s):  
Power Supply ◽  
Power Dissipation ◽  
Supply Voltage ◽  
Focal Plane Arrays ◽  
Input Circuit ◽  
Cmos Process ◽  
Analog To Digital ◽  
Lower Power ◽  
Readout Circuits ◽  
Low Supply Voltage

In this paper, we present a novel, almost-digital approach for bolometer readout circuits to overcome the area and power dissipation bottlenecks of analog-based classical microbolometer circuits. A current-controlled oscillator (CCO)-based analog-to-digital converter (ADC) is utilized instead of a capacitive transimpedance amplifier (CTIA) in the classical readout circuits. This approach, which has not been reported before, both produces the required gain in the bolometer input circuit and directly digitizes the bolometer signal. With the proposed architecture, the need for large capacitances (of the order of 10–15[Formula: see text]pF for each column) at which the current is accumulated in the bolometer circuits and the voltage headroom limitation of classical microbolometer circuits are eliminated. Therefore, the proposed architecture permits to design readout circuits with reduced pixel pitch and lower power supply, both of which in turn lead to higher-resolution Focal Plane Arrays (FPAs) with lower power dissipation. The new architecture is modeled and simulated using a 180-nm CMOS process for sensitivity, noise performance, and power dissipation. Unlike the 3.3-V power supply usage of classical readout circuits, the proposed design utilizes 1.2-V analog and 0.9-V digital supply voltages with a power dissipation of almost half of the classical approach.

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