scholarly journals Design of quaternary logic systems and circuits

2005 ◽  
Vol 18 (1) ◽  
pp. 45-56 ◽  
Author(s):  
Dusanka Bundalo ◽  
Zlatko Bundalo ◽  
Branimir Ðordjevic
Keyword(s):  
Circuit Simulation ◽  
Design Procedure ◽  
Optimization Methods ◽  
Logic Circuits ◽  
Logic Circuit ◽  
Combinational Logic ◽  
Circuit Optimization ◽  
Quaternary Logic ◽  
Operation Conditions ◽  
Logic Systems

The principles and possibilities of design of fully quaternary multiple valued combinational logic systems and circuits are described and proposed in the paper. Different ways of design of fully quaternary combinational logic systems and circuits are considered and described first. Then algorithm for automated computerized design of such systems and circuits is considered and proposed. The algorithm gives possibility for synthesis and optimization of quaternary logic systems and circuits. It is applied on design of CMOS quaternary multiple valued logic systems and circuits. The algorithm includes the most important aspects of design of quaternary logic circuits: logic circuit scheme synthesis and logic circuit optimization. Methods for synthesis of quaternary CMOS combinational logic circuits are proposed and described. Also, method for optimization of CMOS quaternary logic circuits, according to operation conditions and needed characteristics, is proposed and described. Design procedure is realized by personal computer using PSPICE for circuit simulation. Computer PSPICE simulation results confirming described methods and conclusions are given in the paper.

A Fast Simulator in FPGA for LUT-Based Combinational Logic Circuits of Arbitrary Topology for Evolutionary Algorithms

2015 ◽  
Vol 25 (02) ◽  
pp. 1650009
Author(s):  
Daniel Mealha Cabrita ◽  
Carlos Raimundo Erig Lima
Keyword(s):  
Evolutionary Algorithms ◽  
Circuit Simulation ◽  
Logic Circuits ◽  
Combinational Logic ◽  
Limited Data ◽  
Arbitrary Topology ◽  
Circuit Simulator ◽  
Field Programmable ◽  
Combinational Logic Circuits ◽  
Performance Results

Current works on generation of combinational logic circuits (CLC) using evolutionary algorithms (EA) propose solutions using field-programmable gate array (FPGA) to accelerate the process of combinational circuit simulation, a step needed in order to evaluate the level of correctness of each individual circuit. However, the current works fail to separate the two distinct problems: the EA and the circuit simulator. The insistence of treating both problem as a single one results in works that fail to address either properly, restricting solutions to simple circuits and to topologically restrictive circuit simulators, while providing very limited data on the results. In this work, we address the circuit simulator problem exclusively, where we propose an architecture for fast simulation of n-LUT CLC of arbitrary topology. The proposed architecture is modular and makes no assumptions on the specific EA to be used with. We provide detailed performance results for varying circuit dimensions, and those results show that our architecture is able to surpass other works both in terms of performance and topological flexibility.

NOISE-AWARE SPLIT-PATH DOMINO LOGIC AND ITS CLOCK DELAYING SCHEME

2007 ◽  
Vol 16 (01) ◽  
pp. 139-154 ◽  
Author(s):  
DONGKYU PARK ◽  
SEOKSOO YOON ◽  
INHWA JUNG ◽  
CHULWOO KIM
Keyword(s):  
High Speed ◽  
Performance Enhancement ◽  
Circuit Simulation ◽  
Logic Circuits ◽  
Logic Circuit ◽  
Cmos Process ◽  
Total Delay ◽  
Domino Logic ◽  
Delay Cell ◽  
Improved Performance

This paper describes an improved domino logic using split-path (SP) and revised clock-delaying (CD) scheme. SP domino logic is a high-speed operation because it ameliorates the charge-sharing problem by splitting the stacked NMOS transistors used for logic evaluation. Additionally, SP domino logic removes the use of signal ordering. Dual threshold voltage (Vt) assignment methodology for the SP domino logic circuit is also proposed in order to provide the improved performance with low power-consumption overhead. Our experimental results of SP domino logic circuit show that the proposed logic provides the performance improvement up to 15% compared to the conventional domino logic circuit, under the same noise conditions. For further performance enhancement of the domino logic, CD methodology is applied. Moreover, an optimized delay cell is proposed to reduce the clock-delay overhead required to compensate the process, voltage, and temperature (PVT) variations. 32-b Han–Carlson prefix adders using the proposed CD SP domino logic circuits and the conventional CD domino logic circuits were designed to verify the performance enhancement of the proposed circuit. Simulation results show that the total delay of the 32-b adder using the proposed circuit is 454 ps of 5.47FO4 in a 0.18-μm CMOS process.

scholarly journals A New Parameter-Extraction Method for DGS and its Application to the Low-Pass Filter

2004 ◽  
Vol 27 (2) ◽  
pp. 119-123 ◽  
Author(s):  
Haiwen Liu ◽  
Xiaowei Sun ◽  
Zhengfan Li
Keyword(s):  
Equivalent Circuit ◽  
Extraction Method ◽  
Circuit Simulation ◽  
Equivalent Circuit Model ◽  
Design Procedure ◽  
Parameter Extraction ◽  
Defected Ground Structure ◽  
Pass Filter ◽  
Low Pass Filter ◽  
Low Pass

A new and simple parameter-extraction method for the equivalent circuit of defected ground structure (DGS) is presented. Using this method, circuit simulation, based on the DGS equivalent-circuit model, show excellent agreements with the electromagnetic (EM) simulation. Further, our method is applied effectively to design a low-pass filter (LPF) with DGS. Comparison between simulation and measurement confirm the validity of the LPF configuration and design procedure. Simple structure and high power handling capability are obtained from the proposed LPF.

scholarly journals Aero-Thermal Design and Testing of Advanced Turbine Blades

1997 ◽  
Author(s):  
M. Haendler ◽  
D. Raake ◽  
M. Scheurlen
Keyword(s):  
Gas Turbines ◽  
Full Range ◽  
Turbine Blades ◽  
Design Procedure ◽  
Thermal Design ◽  
Test Facility ◽  
Optical Pyrometer ◽  
Electrical Systems ◽  
Operation Conditions ◽  
Improved Performance

Based on the experience gained with more than 80 machines operating worldwide in 50 and 60 Hz electrical systems respectively, Siemens has developed a new generation of advanced gas turbines which yield substantially improved performance at a higher output level. This “3A-Series” comprises three gas turbine models ranging from 70 MW to 240 MW for 50 Hz and 60 Hz power generation applications. The first of the new advanced gas turbines with 170 MW and 3600 rpm was tested in the Berlin factory test facility under the full range of operation conditions. It was equipped with various measurement systems to monitor pressures, gas and metal temperatures, clearances, strains, vibrations and exhaust emissions. This paper presents the aero-thermal design procedure of the highly thermal loaded film cooled first stage blading. The predictions are compared with the extensive optical pyrometer measurements taken at the Siemens test facility on the V84.3A machine under full load conditions. The pyrometer was inserted at several locations in the turbine and radially moved giving a complete surface temperature information of the first stage vanes and blades.

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