Logical gates recognition in a flat transistor circuit

O b j e c t i v e s. With the increasing complexity of verification and simulation of modern VLSI, containing hundreds of millions of transistors, the means of extracting the hierarchical description at the level of logical elements froma flat description of circuits at the transistor level are becoming the main tools for computer-aided design and verification. Decompilation tools for transistor circuits can not only significantly reduce the time to perform VLSI topology check, but also provide the basis for generating test cases, logical reengineering of integrated circuits and reverse engineering to detect untrusted attachments.The objective of the work is to solve the problem of extracting the structure of the functional level from a flat circuit of the transistor level by recognizing in it subcircuits that implement logical elements.M e t h o d s. Graph based methods are proposed for solving some key problems arising at the stage of structural recognition of CMOS gates in a transistor circuit: partitioning a graph into connectivity components corresponding to transistor subcircuits; recognition of subcircuits that are logical elements, and functions implemented by them; forming a library of recognized gates and constructing two-level transistor circuit. The original flat and resulting two-level transistor circuits are presented in SPICE format.Re s u l t s. The proposed methods are implemented in C++ as a part of a transistor circuit decompilation programfor the case without any predetermined cell library. All steps of the proposed methods of structural CMOS gates recognition are performed in a linear time from the number of transistors in the initial circuit.Co n c l u s i o n. The decompilation program has been tested on practical transistor-level circuits. Experiments indicate that the present tool is fast enough to process circuits with more than a hundred thousand transistors in a few minutes on a personal computer. Currently, the authors are developing methods for recognizing more complex elements in a transistor circuit, such as memory elements.

Pair Wise Swapping Based Hypergraph Partitioning Algorithms for VLSI Design

A VLSI integrated circuit is the most significant part of electronic systems such as personal computer or workstation, digital camera, cell phone or a portable computing device, and automobile. So development within the field of electronic space depends on the design planning of VLSI integrated circuit. Circuit partitioning is most important step in VLSI physical design process. Many heuristic partitioning algorithms are proposed for this problem. The first heuristic algorithm for hypergraph partitioning in the domain of VLSI is FM algorithm. In this paper, I have proposed three variations of FM algorithm by utilizing pair insightful swapping strategies. I have played out a relative investigation of FM and my proposed algorithms utilizing two datasets for example ISPD98 and ISPD99. Test results demonstrate that my proposed calculations outflank the FM algorithm.