Sequential circuit fault simulation using logic emulation

A novel approach, called PGEN, is proposed to generate test patterns for resettable or nonresettable synchronous sequential circuits. PGEN contains two major routines, Sequential PODEM (S-PODEM) and a differential fault simulator. Given a fault, S-PODEM uses the concept of multiple time compression supported by a pulsating model, and generates a test vector in a single (yet compressed) time frame. Logic simulation (included in S-PODEM) is invoked to expand the single test vector into a test sequence. The single test vector generation methodology and logic simulation are well coordinated and significantly facilitate sequential circuit test generation. A modified version of differential fault simulation is also implemented and included in PGEN to cover other faults detected by the expanded test sequence. Experiments using computer simulation have been conducted, and results are quite satisfactory.

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A Manual Diagnosis Approach Using Targeted Fault Injection and Fault Simulation to Extend ATPG Diagnostic Resolution in Localizing Faults

ISTFA 2019: Conference Proceedings from the 45th International Symposium for Testing and Failure Analysis ◽

10.31399/asm.cp.istfa2019p0419 ◽

2019 ◽

Author(s):

Rommel Estores ◽

Karo Vander Gucht

Keyword(s):

Fault Injection ◽

Fault Simulation ◽

Fault Localization ◽

Pattern Generation ◽

Test Coverage ◽

Actual Case ◽

Electrical Failure ◽

Starting Point ◽

Diagnostic Resolution ◽

Diagnosis Approach

Abstract This paper discusses a creative manual diagnosis approach, a complementary technique that provides the possibility to extend Automatic Test Pattern Generation (ATPG) beyond its own limits. The authors will discuss this approach in detail using an actual case – a test coverage issue where user-generated ATPG patterns and the resulting ATPG diagnosis isolated the fault to a small part of the digital core. However, traditional fault localization techniques was unable to isolate the fault further. Using the defect candidates from ATPG diagnosis as a starting point, manual diagnosis through fault Injection and fault simulation was performed. Further fault localization was performed using the ‘not detected’ (ND) and/or ‘detected’ (DT) fault classes for each of the available patterns. The result has successfully deduced the defect candidates until the exact faulty net causing the electrical failure was identified. The ability of the FA lab to maximize the use of ATPG in combination with other tools/techniques to investigate failures in detail; is crucial in the fast root cause determination and, in case of a test coverage, aid in having effective test screen method implemented.

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Diagnostic Fault Simulation for the Failure Analyst

ISTFA 2004: Conference Proceedings from the 30th International Symposium for Testing and Failure Analysis ◽

10.31399/asm.cp.istfa2004p0181 ◽

2004 ◽

Author(s):

Dan Bodoh ◽

Anthony Blakely ◽

Terry Garyet

Keyword(s):

Fault Diagnosis ◽

Failure Analysis ◽

Complete Solution ◽

Fault Simulation ◽

Building Blocks ◽

Physical World ◽

Design For Test ◽

Fault Diagnosis System ◽

Diagnosis Algorithm ◽

Diagnosis Tool

Abstract Since failure analysis (FA) tools originated in the design-for-test (DFT) realm, most have abstractions that reflect a designer's viewpoint. These abstractions prevent easy application of diagnosis results in the physical world of the FA lab. This article presents a fault diagnosis system, DFS/FA, which bridges the DFT and FA worlds. First, it describes the motivation for building DFS/FA and how it is an improvement over off-the-shelf tools and explains the DFS/FA building blocks on which the diagnosis tool depends. The article then discusses the diagnosis algorithm in detail and provides an overview of some of the supporting tools that make DFS/FA a complete solution for FA. It also presents a FA example where DFS/FA has been applied. The example demonstrates how the consideration of physical proximity improves the accuracy without sacrificing precision.

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Low Power and High Speed Sequential Circuits Test Architecture

Recent Patents on Computer Science ◽

10.2174/2213275912666191107102512 ◽

2019 ◽

Vol 12 ◽

Author(s):

Ahmed K. Jameil ◽

Yasir Amer Abbas ◽

Saad Al-Azawi

Keyword(s):

Power Consumption ◽

Low Power ◽

Test Generation ◽

High Speed ◽

Fir Filter ◽

Sequential Circuits ◽

Fir Filters ◽

Design Verification ◽

Sequential Circuit ◽

Generation Algorithm

Background: The designed circuits are tested for faults detection in fabrication to determine which devices are defective. The design verification is performed to ensure that the circuit performs the required functions after manufacturing. Design verification is regarded as a test form in both sequential and combinational circuits. The analysis of sequential circuits test is more difficult than in the combinational circuit test. However, algorithms can be used to test any type of sequential circuit regardless of its composition. An important sequential circuit is the finite impulse response (FIR) filters that are widely used in digital signal processing applications. Objective: This paper presented a new design under test (DUT) algorithm for 4-and 8-tap FIR filters. Also, the FIR filter and the proposed DUT algorithm is implemented using field programmable gate arrays (FPGA). Method: The proposed test generation algorithm is implemented in VHDL using Xilinx ISE V14.5 design suite and verified by simulation. The test generation algorithm used FIR filtering redundant faults to obtain a set of target faults for DUT. The fault simulation is used in DUT to assess the benefit of test pattern in fault coverage. Results: The proposed technique provides average reductions of 20 % and 38.8 % in time delay with 57.39 % and 75 % reductions in power consumption and 28.89 % and 28.89 % slices reductions for 4- and 8-tap FIR filter, respectively compared to similar techniques. Conclusions: The results of implementation proved that a high speed and low power consumption design can be achieved. Further, the speed of the proposed architecture is faster than that of existing techniques.

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