Suppression of Quantization Noise for EPWM Transmitter with 2nd-Order Delta-Sigma Modulator

2011 ◽  
Author(s):  
Shinsuke Yokozawa ◽  
Yasushi Yamao
Keyword(s):  
Quantization Noise ◽  
Delta Sigma Modulator ◽  
Delta Sigma

Efficiency Improvement of Delta Sigma Modulator-Based Transmitter Using Complex Delta Sigma Modulator and Noise Reduction Loop

2020 ◽  
Vol 29 (16) ◽  
pp. 2050267
Author(s):  
Nasser Erfani Majd ◽  
Amin Aeenmehr
Keyword(s):  
Noise Reduction ◽  
Average Power ◽  
Quantization Noise ◽  
Coding Efficiency ◽  
Delta Sigma Modulator ◽  
Delta Sigma ◽  
Low Pass ◽  
Polar Low ◽  
Oversampling Ratio

This paper proposes an architecture to enhance coding efficiency (CE) of the Delta Sigma Modulator (DSM) transmitters. In this architecture, a complex–low pass delta sigma modulator (LPDSM) is used instead of existing Cartesian–LPDSM and polar–low pass envelope delta sigma modulator (LPEDSM). Simulation results show that for Uplink long-term evolution (LTE) signal with 1.92[Formula: see text]MHz bandwidth and 7.8-dB peak to average power ratio (PAPR), the CE for the complex–LPDSM-based transmitter is equal to 41.7% in compare to 9.7% CE for Cartesian–LPDSM transmitter. Also, due to the resolving of noise convolution problem, the complex–LPDSM-based transmitter baseband part needs lower oversampling ratio (OSR) and clock speed than polar–LPEDSM transmitter baseband part to achieve the same signal-to-noise and distortion ratio (SNDR). In the next step, a quantization noise reduction loop is implemented in this architecture. By using this technique for an Uplink LTE signal with 1.92[Formula: see text]MHz bandwidth, with the same PAPR and OSR of 16, the CE is improved from 41.7% to 56.1% with 40[Formula: see text]dB SNDR.

Coding Efficiency and Bandwidth Enhancement in Polar Delta-Sigma Modulator Transmitter Using Quantization Noise Reduction and Parallel Processing Techniques

2017 ◽  
Vol 26 (05) ◽  
pp. 1750085 ◽  
Author(s):  
Nasser Erfani Majd ◽  
Hassan Ghafoori Fard ◽  
Abbas Mohammadi
Keyword(s):  
Noise Reduction ◽  
Average Power ◽  
Quantization Noise ◽  
Bandwidth Enhancement ◽  
Coding Efficiency ◽  
Clock Speed ◽  
Delta Sigma Modulator ◽  
Delta Sigma ◽  
Low Pass ◽  
Processing Techniques

This paper introduces an architecture to enhance coding efficiency (CE) and bandwidth of the delta-sigma modulator (DSM) transmitters. In this architecture a low-pass envelope DSM (LPEDSM) is used instead of the traditional Cartesian low-pass DSM (LPDSM) to reduce the quantization noise and to improve the coding efficiency. The simulation results show that for an uplink long-term evolution (LTE) signal with 1.92[Formula: see text]MHz bandwidth, 7.8[Formula: see text]dB peak-to-average power ratio (PAPR), and an oversampling ratio (OSR) of 32, the CE for the polar LPEDSM transmitter is equal to 41.72% in comparison to 9.7% CE for the Cartesian LPDSM transmitter. In the next step, the CE and bandwidth of the transmitter are improved at the same time by using the quantization noise reduction technique in the polar LPEDSM transmitter with parallel baseband. By using this combined technique in the four-branch transmitter baseband part for an uplink LTE signal with 7.68[Formula: see text]MHz bandwidth, 7.8[Formula: see text]dB PAPR, and an OSR of 32, the CE is improved from 42.59% to 55.86% with 40[Formula: see text]dB signal-to-noise-and-distortion ratio (SNDR) while the clock speed is only 61.44[Formula: see text]MHz which is four times lower than the clock speed requirement of the conventional transmitter baseband part to achieve the same SNDR.

A Novel Architecture of Pseudorandom Dithered MASH Digital Delta-Sigma Modulator with Lower Spur

2016 ◽  
Vol 25 (07) ◽  
pp. 1650072
Author(s):  
Seyed Ali Sadat Noori ◽  
Ebrahim Frashidi ◽  
Sirus Sadughi
Keyword(s):  
Quantization Noise ◽  
Noise Shaping ◽  
Constant Input ◽  
Finite Precision ◽  
Delta Sigma Modulator ◽  
Multi Stage ◽  
Delta Sigma ◽  
Spurious Tones ◽  
Finite State ◽  
Novel Method

A Digital Delta Sigma Modulator (DDSM) is a Finite State Machine (FSM); it is implemented using finite precision arithmetic units and the number of available states is finite. The DDSM always produces a periodic output signal when the input is constant. This paper proposes a novel method of applying periodic dither to a DDSM in order to obtain minimized spurious tones. The effects of adding the pseudorandom dither signal in different stages within the proposed Multi-Stage noise Shaping (MASH) modulator are expressed in the equations, and the results are compared. We present results regarding the periodicity of the quantization noise produced by a MASH modulator with a constant input and a pseudorandom dither signal. The performance is confirmed mathematically, and by simulation.

scholarly journals Analysis of Quantization Noise and Power Estimation of Continuous-Time Delta Sigma Analog-to-Digital Converter Using Test Enable Feature For 4G Radios

2018 ◽  
Vol 7 (2) ◽  
pp. 82
Author(s):  
Anil Kumar Sahu ◽  
Vivek Kumar Chandra ◽  
G R Sinha
Keyword(s):  
Low Voltage ◽  
Quantization Noise ◽  
System Level ◽  
Sigma Delta ◽  
Radio System ◽  
Analog To Digital ◽  
Delta Sigma Modulator ◽  
Novel Approach ◽  
Delta Sigma ◽  
Sigma Delta Adc

<span>This paper presents a novel approach for completely test enable feature and low-voltage delta– sigma analog-to-digital (A/D) converters for cutting edge wireless applications. Oversampling feature of ADCs and DACs is enough to meet the requirement related to in-band and adjacent channel leakage ratio (ACLR) execution of 3G/4G portable radio. The quantization noise which is not filtered in ADC is addressed. We have achieved work power-optimization and test enable feature of oversampling ADC is uses in design and simulation so that the problem of quantization error in continues time sigma delta ADC is solved. This paper suggests support to designer for selecting appropriate topologies with various channel arrangements, number of bits and oversampling issues. A test enable feature of CT A/D is presented introducing the test signal generation (TSG) and the COrdinate Rotation Digital Computer (CORDIC) for evaluating the performance of ADC. This helps in addressing the challenge of 4G and upcoming 5G wireless radio. System level plan of a delta–sigma modulator ADC for 4G radios is studied</span><span lang="IN">.</span>

A Long Sequence Length, Reduced Complexity MASH 1-1-1 DDSM for Fractional-N Frequency Synthesizer

2011 ◽  
Vol 130-134 ◽  
pp. 4286-4290
Author(s):  
Bin Li ◽  
Xiang Ning Fan ◽  
Wei Wei Zhu
Keyword(s):  
Output Signal ◽  
Frequency Synthesizer ◽  
Quantization Noise ◽  
Sequence Length ◽  
Third Order ◽  
Delta Sigma Modulator ◽  
Delta Sigma ◽  
Reduced Complexity ◽  
Functional Operation ◽  
State Of Art

In this paper, a long sequence length, reduced complexity MASH 1-1-1 digital delta-sigma modulator (DDSM) suitable for fractional-N frequency synthesizer applications is presented. Good shaping of quantization noise is achieved by using the state of art MASH structure for a digital third-order delta-sigma modulator, meanwhile, the hardware required for this modulator is considerably reduced by recoding all carry output signal from accumulators. The functional operation of the modulator is confirmed by simulation.

A Delta-Sigma Modulator Using a Non-uniform Quantizer Adjusted for the Probability Density of Input Signals

2012 ◽  
Vol E95.B (7) ◽  
pp. 2257-2265
Author(s):  
Toru KITAYABU ◽  
Mao HAGIWARA ◽  
Hiroyasu ISHIKAWA ◽  
Hiroshi SHIRAI
Keyword(s):  
Probability Density ◽  
Delta Sigma Modulator ◽  
Delta Sigma ◽  
Input Signals
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