Granular quantization noise in the first-order delta-sigma modulator

1993 ◽  
Vol 39 (6) ◽  
pp. 1944-1956 ◽  
Author(s):  
I. Galton
Keyword(s):  
Quantization Noise ◽  
First Order ◽  
Delta Sigma Modulator ◽  
Delta Sigma

A novel structure of dithered nested digital delta sigma modulator with low-complexity low-spur for fractional frequency synthesizers

2016 ◽  
Vol 35 (1) ◽  
pp. 157-171 ◽  
Author(s):  
Seyed Ali Sadat Noori ◽  
Ebrahim Farshidi ◽  
Sirus Sadoughi
Keyword(s):  
Frequency Synthesizer ◽  
Frequency Synthesizers ◽  
Linear Feedback ◽  
Hardware Complexity ◽  
Order Error ◽  
Content Type ◽  
First Order ◽  
Fractional Frequency ◽  
Delta Sigma Modulator ◽  
Delta Sigma

Purpose – Digital Delta Sigma Modulator (DDSM) is used widely in electronic circuits including Radars, class-D power amplifiers and fractional frequency synthesizers. The purpose of this paper is to propose an implementation for MASH DDSMs named as Multi Modulus Reduced Complexity (MMRC) architecture. Design/methodology/approach – This architecture will use a very simple pseudorandom Linear Feedback Shift Register (LFSR) dither signal with period N_d to randomize the digital MMRC modulator used for fractional frequency synthesizers. Using error masking methodology, the MMRC modulator can decrease the hardware consumption and increase accuracy of the fractional frequency synthesizer. Rules for selecting the appropriate word lengths of the constituent MMRC modulator are derived. Findings – This paper contains three modulators. The first stage modulator is a variable modulus First Order Error Feedback Modulator and has a programmable modulus M1 that is not a power of two. The second and third stage modulators are the first order pseudorandom LFSR dithered MASH 1-1 and modified MASH 1-1-1, which have conventional modulo M2, M3, respectively. With optimum selection modulus M1, the new structure can synthesize the desired frequency exactly. Simulation results confirm the theoretical predictions. Also the results of circuit implementation proposed method reports 13 per cent reduction in hardware. Originality/value – This paper for the first time proposes a nested sigma delta modulator with a pseudorandom shaped dither signal which reduced hardware complexity and increased the period of output signal. This modulator is exploited in the fractional frequency synthesizer to the output frequency can be set more accurately.

Efficiency Improvement of Delta Sigma Modulator-Based Transmitter Using Complex Delta Sigma Modulator and Noise Reduction Loop

2020 ◽  
Vol 29 (16) ◽  
pp. 2050267
Author(s):  
Nasser Erfani Majd ◽  
Amin Aeenmehr
Keyword(s):  
Noise Reduction ◽  
Average Power ◽  
Quantization Noise ◽  
Coding Efficiency ◽  
Delta Sigma Modulator ◽  
Delta Sigma ◽  
Low Pass ◽  
Polar Low ◽  
Oversampling Ratio

This paper proposes an architecture to enhance coding efficiency (CE) of the Delta Sigma Modulator (DSM) transmitters. In this architecture, a complex–low pass delta sigma modulator (LPDSM) is used instead of existing Cartesian–LPDSM and polar–low pass envelope delta sigma modulator (LPEDSM). Simulation results show that for Uplink long-term evolution (LTE) signal with 1.92[Formula: see text]MHz bandwidth and 7.8-dB peak to average power ratio (PAPR), the CE for the complex–LPDSM-based transmitter is equal to 41.7% in compare to 9.7% CE for Cartesian–LPDSM transmitter. Also, due to the resolving of noise convolution problem, the complex–LPDSM-based transmitter baseband part needs lower oversampling ratio (OSR) and clock speed than polar–LPEDSM transmitter baseband part to achieve the same signal-to-noise and distortion ratio (SNDR). In the next step, a quantization noise reduction loop is implemented in this architecture. By using this technique for an Uplink LTE signal with 1.92[Formula: see text]MHz bandwidth, with the same PAPR and OSR of 16, the CE is improved from 41.7% to 56.1% with 40[Formula: see text]dB SNDR.

A 10-Gb/s Receiver With Track-and-Hold-Type Linear Phase Detector and Charge-Redistribution First-Order $\Delta\Sigma$ Modulator in 90-nm CMOS

2009 ◽  
Vol 44 (12) ◽  
pp. 3539-3546 ◽  
Author(s):  
Koji Fukuda ◽  
Hiroki Yamashita ◽  
Fumio Yuki ◽  
Goichi Ono ◽  
Ryo Nemoto ◽  
...  
Keyword(s):  
Phase Detector ◽  
Linear Phase ◽  
Charge Redistribution ◽  
First Order ◽  
Delta Sigma Modulator ◽  
Delta Sigma

Coding Efficiency and Bandwidth Enhancement in Polar Delta-Sigma Modulator Transmitter Using Quantization Noise Reduction and Parallel Processing Techniques

2017 ◽  
Vol 26 (05) ◽  
pp. 1750085 ◽  
Author(s):  
Nasser Erfani Majd ◽  
Hassan Ghafoori Fard ◽  
Abbas Mohammadi
Keyword(s):  
Noise Reduction ◽  
Average Power ◽  
Quantization Noise ◽  
Bandwidth Enhancement ◽  
Coding Efficiency ◽  
Clock Speed ◽  
Delta Sigma Modulator ◽  
Delta Sigma ◽  
Low Pass ◽  
Processing Techniques

This paper introduces an architecture to enhance coding efficiency (CE) and bandwidth of the delta-sigma modulator (DSM) transmitters. In this architecture a low-pass envelope DSM (LPEDSM) is used instead of the traditional Cartesian low-pass DSM (LPDSM) to reduce the quantization noise and to improve the coding efficiency. The simulation results show that for an uplink long-term evolution (LTE) signal with 1.92[Formula: see text]MHz bandwidth, 7.8[Formula: see text]dB peak-to-average power ratio (PAPR), and an oversampling ratio (OSR) of 32, the CE for the polar LPEDSM transmitter is equal to 41.72% in comparison to 9.7% CE for the Cartesian LPDSM transmitter. In the next step, the CE and bandwidth of the transmitter are improved at the same time by using the quantization noise reduction technique in the polar LPEDSM transmitter with parallel baseband. By using this combined technique in the four-branch transmitter baseband part for an uplink LTE signal with 7.68[Formula: see text]MHz bandwidth, 7.8[Formula: see text]dB PAPR, and an OSR of 32, the CE is improved from 42.59% to 55.86% with 40[Formula: see text]dB signal-to-noise-and-distortion ratio (SNDR) while the clock speed is only 61.44[Formula: see text]MHz which is four times lower than the clock speed requirement of the conventional transmitter baseband part to achieve the same SNDR.

A Novel Architecture of Pseudorandom Dithered MASH Digital Delta-Sigma Modulator with Lower Spur

2016 ◽  
Vol 25 (07) ◽  
pp. 1650072
Author(s):  
Seyed Ali Sadat Noori ◽  
Ebrahim Frashidi ◽  
Sirus Sadughi
Keyword(s):  
Quantization Noise ◽  
Noise Shaping ◽  
Constant Input ◽  
Finite Precision ◽  
Delta Sigma Modulator ◽  
Multi Stage ◽  
Delta Sigma ◽  
Spurious Tones ◽  
Finite State ◽  
Novel Method

A Digital Delta Sigma Modulator (DDSM) is a Finite State Machine (FSM); it is implemented using finite precision arithmetic units and the number of available states is finite. The DDSM always produces a periodic output signal when the input is constant. This paper proposes a novel method of applying periodic dither to a DDSM in order to obtain minimized spurious tones. The effects of adding the pseudorandom dither signal in different stages within the proposed Multi-Stage noise Shaping (MASH) modulator are expressed in the equations, and the results are compared. We present results regarding the periodicity of the quantization noise produced by a MASH modulator with a constant input and a pseudorandom dither signal. The performance is confirmed mathematically, and by simulation.

Sign in / Sign up

Export Citation Format

Share Document