An area-efficient design for Programmable memory Built-In Self-Test

2008 ◽  
Author(s):  
Chung-Fu Lin ◽  
Yeong-Jar Chang
Keyword(s):  
Efficient Design ◽  
Self Test ◽  
Built In Self Test ◽  
Area Efficient

Design for Testability of High-Speed Advance Multipliers

2020 ◽  
pp. 175-190
Author(s):  
Suman Lata Tripathi
Keyword(s):  
High Speed ◽  
High Performance ◽  
Design For Testability ◽  
Online Testing ◽  
Efficient Design ◽  
Self Test ◽  
Built In Self Test ◽  
Work Done ◽  
Testing Work ◽  
Circuit Under Test

An efficient design for testability (DFT) has been a major thrust of area for today's VLSI engineers. A poorly designed DFT would result in losses for manufacturers with a considerable rework for the designers. BIST (built-in self-test), one of the promising DFT techniques, is rapidly modifying with the advances in technology as the device shrinks. The increasing complexities of the hardware have shifted the trend to include BISTs in high performance circuitry for offline as well as online testing. Work done here involves testing a circuit under test (CUT) with built in response analyser and vector generator with a monitor to control all the activities.

An Area-Efficient High-Resolution Segmented Σ Δ -DAC for Built-In Self-Test Applications

2021 ◽  
pp. 1-14
Author(s):  
Ahmed S. Emara ◽  
Denis Romanov ◽  
Gordon W. Roberts ◽  
Sadok Aouini ◽  
Soheyl Ziabakhsh ◽  
...  
Keyword(s):  
High Resolution ◽  
Self Test ◽  
Built In Self Test ◽  
Area Efficient

RF Phase Error Built-In-Self-Test for A GSM SOC

2008 ◽  
Vol 1 (4) ◽  
pp. 39-44
Author(s):  
Dallas Webster ◽  
Loi Phan ◽  
Oren Eliezer ◽  
Rick Hudgens ◽  
Donald Lie
Keyword(s):  
Phase Error ◽  
Self Test ◽  
Built In Self Test

Fault-based Built-in Self-test and Evaluation of Phase Locked Loops

2021 ◽  
Vol 26 (3) ◽  
pp. 1-18
Author(s):  
Mehmet Ince ◽  
Ender Yilmaz ◽  
Wei Fu ◽  
Joonsung Park ◽  
Krishnaswamy Nagaraj ◽  
...  
Keyword(s):  
Phase Locked Loops ◽  
Test And Evaluation ◽  
Self Test ◽  
Built In Self Test
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