FPGA-based switch-level fault emulation using modular-based dynamic partial reconfiguration

Fault simulation is a process of purposely injecting faults into a target circuit and observing a circuit's behavior in the presence of faulty logic. This observation helps designers to implement certain fault tolerance schemes thereby combating hardware failures. Fault simulation in most implementations has until now been software-based. Several fault emulation approaches have been proposed to accelerate fault simulation process using FPGA. There are generally two types of hardware fault injection: injector-based and reconfiguration-based. Injector-based methods require inserting fault injector circuitry into the circuit under test thus adding hardware overhead. On the other hand, reconfigurable-based methods require much less hardware overhead. However, these methods may be very slow because reconfiguring an entire FPGA device can take several seconds. This long confirmation time is usually the bottleneck of the emulation system. This project proposes a novel switch-level fault emulation system utilizing FPGA modular-based dynamic partial reconfiguration (DPR). In the proposed approach, faults are modeled at switch-level for an accurate fault list and mapped to gate-level for efficient synthesis. In addition, circuit-under-test is partitioned using an unbalanced tree structure to facilitate modular-based DPR. Modular-based DPR partitions a design into modules, and each module can be reconfigured independently without shutting down the FPGA. This capability is applied to fault injection where each circuit partition can be reconfigured individually without erasing the rest of FPGA. First a partial configuration bitstream representing the faulty partition is created. Fault injection can then be performed by downloading only this partial bitstream to FPGA, thereby eliminating the need for full-device reconfiguration and therefore reducing fault emulation runtime. This report presents both a theoretical explanation and the implementation details regarding this approach. Experimental results are also be provided. [sic]

FPGA-based switch-level fault emulation using modular-based dynamic partial reconfiguration

Fault simulation is a process of purposely injecting faults into a target circuit and observing a circuit's behavior in the presence of faulty logic. This observation helps designers to implement certain fault tolerance schemes thereby combating hardware failures. Fault simulation in most implementations has until now been software-based. Several fault emulation approaches have been proposed to accelerate fault simulation process using FPGA. There are generally two types of hardware fault injection: injector-based and reconfiguration-based. Injector-based methods require inserting fault injector circuitry into the circuit under test thus adding hardware overhead. On the other hand, reconfigurable-based methods require much less hardware overhead. However, these methods may be very slow because reconfiguring an entire FPGA device can take several seconds. This long confirmation time is usually the bottleneck of the emulation system. This project proposes a novel switch-level fault emulation system utilizing FPGA modular-based dynamic partial reconfiguration (DPR). In the proposed approach, faults are modeled at switch-level for an accurate fault list and mapped to gate-level for efficient synthesis. In addition, circuit-under-test is partitioned using an unbalanced tree structure to facilitate modular-based DPR. Modular-based DPR partitions a design into modules, and each module can be reconfigured independently without shutting down the FPGA. This capability is applied to fault injection where each circuit partition can be reconfigured individually without erasing the rest of FPGA. First a partial configuration bitstream representing the faulty partition is created. Fault injection can then be performed by downloading only this partial bitstream to FPGA, thereby eliminating the need for full-device reconfiguration and therefore reducing fault emulation runtime. This report presents both a theoretical explanation and the implementation details regarding this approach. Experimental results are also be provided. [sic]

Adaptive random testing with total cartesian distance for black box circuit under test

<p>Testing and verification of digital circuits is of vital importance in electronics industry. Moreover, key designs require preservation of their intellectual property that might restrict access to the internal structure of circuit under test. Random testing is a classical solution to black box testing as it generates test patterns without using the structural implementation of the circuit under test. However, random testing ignores the importance of previously applied test patterns while generating subsequent test patterns. An improvement to random testing is Antirandom that diversifies every subsequent test pattern in the test sequence. Whereas, computational intensive process of distance calculation restricts its scalability for large input circuit under test. Fixed sized candidate set adaptive random testing uses predetermined number of patterns for distance calculations to avoid computational complexity. A combination of max-min distance with previously executed patterns is carried out for each test pattern candidate. However, the reduction in computational complexity reduces the effectiveness of test set in terms of fault coverage. This paper uses a total cartesian distance based approach on fixed sized candidate set to enhance diversity in test sequence. The proposed approach has a two way effect on the test pattern generation as it lowers the computational intensity along with enhancement in the fault coverage. Fault simulation results on ISCAS’85 and ISCAS’89 benchmark circuits show that fault coverage of the proposed method increases up to 20.22% compared to previous method.</p>

X-Sand Filter: An X-Tolerant Response Compaction Technique for Faster-Than-At-Speed Testing

Faster-than-at-speed testing provides an effective way of detecting small delay defects but at the cost of increased number of unknown logic values on longer paths of the circuit under test. For efficient testing, these unknown logic values need to be filtered out of the circuit under test output. In past, different compaction hardware schemes were presented to minimize these unknown logic values, all these schemes were effective in handling a limited number of unknown values arising due to design imperfections, processing problems manufacturing problems material problems etc. but no effective compaction scheme is available to handle large number of these logic values arising due to faster-than-at-speed testing. This paper presents “X-sand filter”, a compaction technique, an extension of already presented idea of “X-tolerant signature analysis”. Here, the idea of “X-tolerant signature analysis” with modifications has been applied and has attained a considerable improvement in the X-tolerance. X-sand filter is a hierarchical structure that handles gradual X-density reduction in an efficient manner. Simulation results obtained show that we can achieve up to 90 % reduction in the X-density if we use X-sand filter. Extensions to the work of X-sand filter can be carried out in future to enhance its capabilities and make its configuration more flexible in terms of layer designing.

X-Sand Filter: An X-Tolerant Response Compaction Technique for Faster-Than-At-Speed Testing

Faster-than-at-speed testing provides an effective way of detecting small delay defects but at the cost of increased number of unknown logic values on longer paths of the circuit under test. For efficient testing, these unknown logic values need to be filtered out of the circuit under test output. In past, different compaction hardware schemes were presented to minimize these unknown logic values, all these schemes were effective in handling a limited number of unknown values arising due to design imperfections, processing problems manufacturing problems material problems etc. but no effective compaction scheme is available to handle large number of these logic values arising due to faster-than-at-speed testing. This paper presents “X-sand filter”, a compaction technique, an extension of already presented idea of “X-tolerant signature analysis”. Here, the idea of “X-tolerant signature analysis” with modifications has been applied and has attained a considerable improvement in the X-tolerance. X-sand filter is a hierarchical structure that handles gradual X-density reduction in an efficient manner. Simulation results obtained show that we can achieve up to 90 % reduction in the X-density if we use X-sand filter. Extensions to the work of X-sand filter can be carried out in future to enhance its capabilities and make its configuration more flexible in terms of layer designing.

Area Efficient Design of BIST Technique in UART using Circuit under Test (CUT)

Multiplication float of IC exchange, numerous microchips are demonstrated in a foundry. The nearness of carrying on inbuilt equipment Trojans (HTs) is of tight security worry, without the attention to end clients or unique originators of a host, to distinguish sans trojans circuit. For this creator looks for low exchanging likelihood nets to embed HTs to lessen control spillage. However, the circuit's net encounters a particular state and turning probabilities on test and capacity mode. The proposed strategy, quick heuristic, is incited on circuit under test (CUT). This is an insignificant mind-boggling, high exact, famous standard and complex circuit tried with sensible deferral. In equipment self-testing, (worked in individual test) offer a commendable answer for lessens item disappointment, intricacy happens in multiplication. Plan and incitation of all-inclusive offbeat collector transmitter (UART), to diminish control, territory, to arrive at convenient, steady and dependable information transmission is utilized.

Design for Testability of High-Speed Advance Multipliers

An efficient design for testability (DFT) has been a major thrust of area for today's VLSI engineers. A poorly designed DFT would result in losses for manufacturers with a considerable rework for the designers. BIST (built-in self-test), one of the promising DFT techniques, is rapidly modifying with the advances in technology as the device shrinks. The increasing complexities of the hardware have shifted the trend to include BISTs in high performance circuitry for offline as well as online testing. Work done here involves testing a circuit under test (CUT) with built in response analyser and vector generator with a monitor to control all the activities.

Fuente Didáctica de Voltaje Lineal

A voltage source is a very useful and necessary tool in prototype testing of electronics projects, especially when they need to be tested in a controlled and safe environment both for the circuit being tested and for the user who is Operating the voltage source. The following article presents a new innovation of this type of tool, it is a linear voltage source with self-protection system for both the user and the circuit under test, it consists of level detecting circuits placed in each voltage regulator which will notify the user if any type of short circuit occurs during the testing stage of their prototype. The user will be notified by the same voltage source by means of a light that will indicate the status of the test, all this in order to avoid short circuit damage and its serious consequences.

DC Hard Faults Detection and Localization in Analog Circuits Using Fuzzy Logic Techniques

This paper demonstrates a novel technique based on the use of a fuzzy logic system and the simulation before test (SBT) approach for hard faults detection and localization in analog electronic circuits comprising bipolar transistors. For this purpose, first, simulations of the circuit under test (CUT) are performed before the test stage by investigating the response of the circuit under test in faulty and fault-free conditions. Following this, two signatures parameters—output voltage and supply current—are observed and used for the fault diagnosis; the CUT is simulated using the OrCAD/PSpice software, and the output is analyzed in the DC domain. This method is validated through an inverter amplifier based on the uA741 operational amplifier. Then the results of different experiments are presented to demonstrate the applicability of the proposed method by increasing its efficiency.