Robust Cu Dual Damascene Interconnects With Porous SiOCH Films Fabricated by Low-Damage Multi-Hard-Mask Etching Technology

2006 ◽  
Vol 19 (4) ◽  
pp. 455-464 ◽  
Author(s):  
H. Ohtake ◽  
M. Tagami ◽  
M. Tada ◽  
M. Ueki ◽  
M. Abe ◽  
...  
Keyword(s):  
Hard Mask ◽  
Dual Damascene ◽  
Mask Etching ◽  
Damascene Interconnects

scholarly journals Fatal Void Size Comparisons in Via-Below and Via-Above Cu Dual-Damascene Interconnects

2004 ◽  
Vol 812 ◽  
Author(s):  
Z. -S. Choi ◽  
C. L. Gan ◽  
F. Wei ◽  
C. V. Thompson ◽  
J. H. Lee ◽  
...  
Keyword(s):  
Numerical Simulation ◽  
Failure Mechanisms ◽  
Simulation Tool ◽  
Void Size ◽  
Dual Damascene ◽  
Preferential Nucleation ◽  
Failure Correlation ◽  
Void Volumes ◽  
Damascene Interconnects ◽  
Critical Void

AbstractThe median-times-to-failure (t50's) for straight dual-damascene via-terminated copper interconnect structures, tested under the same conditions, depend on whether the vias connect down to underlaying leads (metal 2, M2, or via-below structures) or connect up to overlaying leads (metal 1, M1, or via-above structures). Experimental results for a variety of line lengths, widths, and numbers of vias show higher t50's for M2 structures than for analogous M1 structures. It has been shown that despite this asymmetry in lifetimes, the electromigration drift velocity is the same for these two types of structures, suggesting that fatal void volumes are different in these two cases. A numerical simulation tool based on the Korhonen model has been developed and used to simulate the conditions for void growth and correlate fatal void sizes with lifetimes. These simulations suggest that the average fatal void size for M2 structures is more than twice the size of that of M1 structures. This result supports an earlier suggestion that preferential nucleation at the Cu/Si3N4 interface in both M1 and M2 structures leads to different fatal void sizes, because larger voids are required to span the line thickness in M2 structures while smaller voids below the base of vias can cause failures in M1 structures. However, it is also found that the fatal void sizes corresponding to the shortest-times-to-failure (STTF's) are similar for M1 and M2, suggesting that the voids that lead to the shortest lifetimes occur at or in the vias in both cases, where a void need only span the via to cause failure. Correlation of lifetimes and critical void volumes provides a useful tool for distinguishing failure mechanisms.

A thick CESL stressed ultra-small (Lg=40nm) SiGe-channel MOSFET fabricated with 193nm scanner lithography and TEOS hard mask etching

2007 ◽  
Author(s):  
Wen-Shiang Liao ◽  
Tung-Hung Chen ◽  
Hsin-Hung Lin ◽  
Wen-Tung Chang ◽  
Tommy Shih ◽  
...  
Keyword(s):  
Hard Mask ◽  
Mask Etching

The Role of Oxygen on Anisotropy in Chromium Oxide Hard Mask Etching for Sub-Micron Fabrication

2021 ◽  
Vol 20 ◽  
pp. 33-38
Author(s):  
Huseyin Ekinci ◽  
Navid M.S. Jahed ◽  
Mohammad Soltani ◽  
Bo Cui
Keyword(s):  
Chromium Oxide ◽  
Hard Mask ◽  
Mask Etching
Sign in / Sign up

Export Citation Format

Share Document