Speeding up VLSI Layout Verification Using Fuzzy Attributed Graphs Approach

Nian Zhang; Donald C. Wunsch II

doi:10.1109/tfuzz.2006.877358

Speeding up VLSI Layout Verification Using Fuzzy Attributed Graphs Approach

IEEE Transactions on Fuzzy Systems ◽

10.1109/tfuzz.2006.877358 ◽

2006 ◽

Vol 14 (6) ◽

pp. 728-737 ◽

Cited By ~ 6

Author(s):

Nian Zhang ◽

Donald C. Wunsch II

Keyword(s):

Vlsi Layout ◽

Attributed Graphs ◽

Layout Verification

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Boundary element methods for 3D capacitance and substrate resistance calculations in inhomogeneous media in a VLSI layout verification package

Advances in Engineering Software ◽

10.1016/0965-9978(94)90027-2 ◽

1994 ◽

Vol 20 (1) ◽

pp. 19-27 ◽

Cited By ~ 26

Author(s):

T. Smedes ◽

N.P. van der Meijs ◽

A.J. van Genderen

Keyword(s):

Boundary Element ◽

Inhomogeneous Media ◽

Boundary Element Methods ◽

Vlsi Layout ◽

Layout Verification ◽

Substrate Resistance

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RISCE-a reduced instruction set circuit extractor for hierarchical VLSI layout verification based on interaction rules

10.1109/cicc.1988.20818 ◽

2003 ◽

Cited By ~ 2

Author(s):

V. Henkel ◽

U. Golze

Keyword(s):

Instruction Set ◽

Vlsi Layout ◽

Layout Verification

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Parallel Algorithms for VLSI Layout Verification

Journal of Parallel and Distributed Computing ◽

10.1006/jpdc.1996.0096 ◽

1996 ◽

Vol 36 (2) ◽

pp. 156-172 ◽

Cited By ~ 3

Author(s):

Ky MacPherson ◽

Prithviraj Banerjee

Keyword(s):

Parallel Algorithms ◽

Vlsi Layout ◽

Layout Verification

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A PC knowledge-based environment for VLSI layout verification

Journal of Systems and Software ◽

10.1016/0164-1212(92)90044-k ◽

1992 ◽

Vol 18 (1) ◽

pp. 19-31

Author(s):

F. Hashim ◽

S.E.-D. Habib ◽

M. Zaki

Keyword(s):

Vlsi Layout ◽

Knowledge Based ◽

Layout Verification

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A logic-to-logic comparator for VLSI layout verification

IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems ◽

10.1109/43.3221 ◽

1988 ◽

Vol 7 (8) ◽

pp. 897-907 ◽

Cited By ~ 5

Author(s):

P.M. Maurer ◽

A.D. Schapira

Keyword(s):

Vlsi Layout ◽

Layout Verification

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Automatic VLSI Layout Verification

10.1109/dac.1981.1585438 ◽

1981 ◽

Cited By ~ 6

Author(s):

L. Williams

Keyword(s):

Vlsi Layout ◽

Layout Verification

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Effective and Scalable Clustering on Massive Attributed Graphs

Proceedings of the Web Conference 2021 ◽

10.1145/3442381.3449875 ◽

2021 ◽

Author(s):

Renchi Yang ◽

Jieming Shi ◽

Yin Yang ◽

Keke Huang ◽

Shiqi Zhang ◽

...

Keyword(s):

Scalable Clustering ◽

Attributed Graphs

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An Optimum Channel Routing Algorithm in the Knock-knee Diagonal Model

VLSI Design ◽

10.1155/1994/19638 ◽

1994 ◽

Vol 1 (3) ◽

pp. 233-242 ◽

Cited By ~ 1

Author(s):

Xiaoyu Song

Keyword(s):

Routing Algorithm ◽

Difficult Problem ◽

Layout Design ◽

Channel Routing ◽

Routing Problem ◽

Vlsi Layout ◽

Channel Density ◽

Optimum Algorithm ◽

Important Time ◽

Optimum Channel

Channel routing problem is an important, time consuming and difficult problem in VLSI layout design. In this paper, we consider the two-terminal channel routing problem in a new routing model, called knock-knee diagonal model, where the grid consists of right and left tracks displayed at +45° and –45°. An optimum algorithm is presented, which obtains d + 1 as an upper bound to the channel width, where d is the channel density.

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