A logic-to-logic comparator for VLSI layout verification

1988 ◽  
Vol 7 (8) ◽  
pp. 897-907 ◽  
Author(s):  
P.M. Maurer ◽  
A.D. Schapira
Keyword(s):  
Vlsi Layout ◽  
Layout Verification

Parallel Algorithms for VLSI Layout Verification

1996 ◽  
Vol 36 (2) ◽  
pp. 156-172 ◽  
Author(s):  
Ky MacPherson ◽  
Prithviraj Banerjee
Keyword(s):  
Parallel Algorithms ◽  
Vlsi Layout ◽  
Layout Verification

A PC knowledge-based environment for VLSI layout verification

1992 ◽  
Vol 18 (1) ◽  
pp. 19-31
Author(s):  
F. Hashim ◽  
S.E.-D. Habib ◽  
M. Zaki
Keyword(s):  
Vlsi Layout ◽  
Knowledge Based ◽  
Layout Verification

scholarly journals An Optimum Channel Routing Algorithm in the Knock-knee Diagonal Model

VLSI Design ◽  
1994 ◽  
Vol 1 (3) ◽  
pp. 233-242 ◽  
Author(s):  
Xiaoyu Song
Keyword(s):  
Routing Algorithm ◽  
Difficult Problem ◽  
Layout Design ◽  
Channel Routing ◽  
Routing Problem ◽  
Vlsi Layout ◽  
Channel Density ◽  
Optimum Algorithm ◽  
Important Time ◽  
Optimum Channel

Channel routing problem is an important, time consuming and difficult problem in VLSI layout design. In this paper, we consider the two-terminal channel routing problem in a new routing model, called knock-knee diagonal model, where the grid consists of right and left tracks displayed at +45° and –45°. An optimum algorithm is presented, which obtains d + 1 as an upper bound to the channel width, where d is the channel density.

Hierarchical detailed floorplanning with global routing in VLSI layout design

1991 ◽  
Vol 74 (10) ◽  
pp. 85-95
Author(s):  
Michiroh Ohmura ◽  
Shin'Ichi Wakabayashi ◽  
Jun'Ichi Miyao ◽  
Noriyoshi Yoshida
Keyword(s):  
Layout Design ◽  
Global Routing ◽  
Vlsi Layout
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