Parallel Algorithms for VLSI Layout Verification

Ky MacPherson; Prithviraj Banerjee

doi:10.1006/jpdc.1996.0096

Parallel Algorithms for VLSI Layout Verification

Journal of Parallel and Distributed Computing ◽

10.1006/jpdc.1996.0096 ◽

1996 ◽

Vol 36 (2) ◽

pp. 156-172 ◽

Cited By ~ 3

Author(s):

Ky MacPherson ◽

Prithviraj Banerjee

Keyword(s):

Parallel Algorithms ◽

Vlsi Layout ◽

Layout Verification

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Boundary element methods for 3D capacitance and substrate resistance calculations in inhomogeneous media in a VLSI layout verification package

Advances in Engineering Software ◽

10.1016/0965-9978(94)90027-2 ◽

1994 ◽

Vol 20 (1) ◽

pp. 19-27 ◽

Cited By ~ 26

Author(s):

T. Smedes ◽

N.P. van der Meijs ◽

A.J. van Genderen

Keyword(s):

Boundary Element ◽

Inhomogeneous Media ◽

Boundary Element Methods ◽

Vlsi Layout ◽

Layout Verification ◽

Substrate Resistance

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RISCE-a reduced instruction set circuit extractor for hierarchical VLSI layout verification based on interaction rules

10.1109/cicc.1988.20818 ◽

2003 ◽

Cited By ~ 2

Author(s):

V. Henkel ◽

U. Golze

Keyword(s):

Instruction Set ◽

Vlsi Layout ◽

Layout Verification

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A PC knowledge-based environment for VLSI layout verification

Journal of Systems and Software ◽

10.1016/0164-1212(92)90044-k ◽

1992 ◽

Vol 18 (1) ◽

pp. 19-31

Author(s):

F. Hashim ◽

S.E.-D. Habib ◽

M. Zaki

Keyword(s):

Vlsi Layout ◽

Knowledge Based ◽

Layout Verification

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Speeding up VLSI Layout Verification Using Fuzzy Attributed Graphs Approach

IEEE Transactions on Fuzzy Systems ◽

10.1109/tfuzz.2006.877358 ◽

2006 ◽

Vol 14 (6) ◽

pp. 728-737 ◽

Cited By ~ 6

Author(s):

Nian Zhang ◽

Donald C. Wunsch II

Keyword(s):

Vlsi Layout ◽

Attributed Graphs ◽

Layout Verification

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A logic-to-logic comparator for VLSI layout verification

IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems ◽

10.1109/43.3221 ◽

1988 ◽

Vol 7 (8) ◽

pp. 897-907 ◽

Cited By ~ 5

Author(s):

P.M. Maurer ◽

A.D. Schapira

Keyword(s):

Vlsi Layout ◽

Layout Verification

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Automatic VLSI Layout Verification

10.1109/dac.1981.1585438 ◽

1981 ◽

Cited By ~ 6

Author(s):

L. Williams

Keyword(s):

Vlsi Layout ◽

Layout Verification

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Parallel algorithms and domain decomposition technologies for solving three-dimensional boundary value problems on quasi-structured grids

Сибирский журнал вычислительной математики ◽

10.15372/sjnm20160205 ◽

2016 ◽

Keyword(s):

Parallel Algorithms ◽

Domain Decomposition ◽

Boundary Value Problems ◽

Boundary Value ◽

Three Dimensional ◽

Structured Grids ◽

Dimensional Boundary

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Parallel algorithms for three-dimensional parabolic and pseudoparabolic problems with different boundary conditions

Nonlinear Analysis Modelling and Control ◽

10.15388/na.2014.3.5 ◽

2014 ◽

Vol 19 (3) ◽

pp. 382-395 ◽

Cited By ~ 4

Author(s):

Raimondas Čiegis ◽

◽

Olga Suboč ◽

Andrej Bugajev

Keyword(s):

Boundary Conditions ◽

Parallel Algorithms ◽

Three Dimensional ◽

Different Boundary Conditions

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Multilevel Algebraic Approach for Performance Analysis of Parallel Algorithms

Computing and Informatics ◽

10.31577/cai_2019_4_817 ◽

2019 ◽

Vol 38 (4) ◽

pp. 817-850 ◽

Cited By ~ 8

Author(s):

Luisa D'Amore ◽

Valeria Mele ◽

Diego Romano ◽

Giuliano Laccetti

Keyword(s):

Performance Analysis ◽

Parallel Algorithms ◽

Algebraic Approach

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Performance Evaluation of Parallel Algorithms and Architectures in Concurrent Multiprocessor Systems

10.21236/ada203982 ◽

1988 ◽

Author(s):

H. H. Ammar ◽

Y. S. Fong ◽

R. Mukundan ◽

C. A. Pomalaza-Raez

Keyword(s):

Performance Evaluation ◽

Parallel Algorithms ◽

Multiprocessor Systems ◽

Parallel Algorithms And Architectures

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