scholarly journals An Optimum Channel Routing Algorithm in the Knock-knee Diagonal Model

VLSI Design ◽  
1994 ◽  
Vol 1 (3) ◽  
pp. 233-242 ◽  
Author(s):  
Xiaoyu Song
Keyword(s):  
Routing Algorithm ◽  
Difficult Problem ◽  
Layout Design ◽  
Channel Routing ◽  
Routing Problem ◽  
Vlsi Layout ◽  
Channel Density ◽  
Optimum Algorithm ◽  
Important Time ◽  
Optimum Channel

Channel routing problem is an important, time consuming and difficult problem in VLSI layout design. In this paper, we consider the two-terminal channel routing problem in a new routing model, called knock-knee diagonal model, where the grid consists of right and left tracks displayed at +45° and –45°. An optimum algorithm is presented, which obtains d + 1 as an upper bound to the channel width, where d is the channel density.

INTEGRATED CIRCUIT CHANNEL ROUTING USING A PARETO-OPTIMAL GENETIC ALGORITHM

2012 ◽  
Vol 21 (05) ◽  
pp. 1250041
Author(s):  
THEODORE W. MANIKAS
Keyword(s):  
Integrated Circuit ◽  
Routing Algorithm ◽  
Signal Propagation ◽  
Pareto Optimal ◽  
Signal Delay ◽  
Integrated Circuit Design ◽  
Channel Routing ◽  
Routing Problem ◽  
Propagation Delays ◽  
Optimal Approach

An important part of the integrated circuit design process is the channel routing stage, which determines how to interconnect components that are arranged in sets of rows. The channel routing problem has been shown to be NP-complete, thus this problem is often solved using genetic algorithms. The traditional objective for most channel routers is to minimize total area required to complete routing. However, another important objective is to minimize signal propagation delays in the circuit. This paper describes the development of a genetic channel routing algorithm that uses a Pareto-optimal approach to accommodate both objectives. When compared to the traditional channel routing approach, the new channel router produced layouts with decreased signal delay, while still minimizing routing area.

Hierarchical detailed floorplanning with global routing in VLSI layout design

1991 ◽  
Vol 74 (10) ◽  
pp. 85-95
Author(s):  
Michiroh Ohmura ◽  
Shin'Ichi Wakabayashi ◽  
Jun'Ichi Miyao ◽  
Noriyoshi Yoshida
Keyword(s):  
Layout Design ◽  
Global Routing ◽  
Vlsi Layout

PERMUTATION ROUTING AND SORTING ON THE RECONFIGURABLE MESH

1998 ◽  
Vol 09 (02) ◽  
pp. 199-211
Author(s):  
SANGUTHEVAR RAJASEKARAN ◽  
THEODORE MCKENDALL
Keyword(s):  
Lower Bound ◽  
Randomized Algorithms ◽  
Linear Array ◽  
Order Term ◽  
Routing Algorithm ◽  
Sorting Algorithm ◽  
Routing Problem ◽  
Reconfigurable Mesh ◽  
Permutation Routing ◽  
Time Bounds

In this paper we demonstrate the power of reconfiguration by presenting efficient randomized algorithms for both packet routing and sorting on a reconfigurable mesh connected computer. The run times of these algorithms are better than the best achievable time bounds on a conventional mesh. Many variations of the reconfigurable mesh can be found in the literature. We define yet another variation which we call as Mr. We also make use of the standard PARBUS model. We show that permutation routing problem can be solved on a linear array Mr of size n in [Formula: see text] steps, whereas n-1 is the best possible run time without reconfiguration. A trivial lower bound for routing on Mr will be [Formula: see text]. On the PARBUS linear array, n is a lower bound and hence any standard n-step routing algorithm will be optimal. We also show that permutation routing on an n×n reconfigurable mesh Mr can be done in time n+o(n) using a randomized algorithm or in time 1.25n+o(n) deterministically. In contrast, 2n-2 is the diameter of a conventional mesh and hence routing and sorting will need at least 2n-2 steps on a conventional mesh. A lower bound of [Formula: see text] is in effect for routing on the 2D mesh Mr as well. On the other hand, n is a lower bound for routing on the PARBUS and our algorithms have the same time bounds on the PARBUS as well. Thus our randomized routing algorithm is optimal upto a lower order term. In addition we show that the problem of sorting can be solved in randomized time n+o(n) on Mr as well as on PARBUS. Clearly, this sorting algorithm will be optimal on the PARBUS model. The time bounds of our randomized algorithms hold with high probability.

An Automated Layout Design System for Industrial Plant Piping

1991 ◽  
Author(s):  
N. Narikawa ◽  
S. Fujimoto ◽  
N. Sasaki ◽  
S. Azuma
Keyword(s):  
Expert Knowledge ◽  
Routing Algorithm ◽  
Layout Design ◽  
Memory Storage ◽  
Industrial Plant ◽  
Design System ◽  
Small Computer ◽  
Phase Step ◽  
New Approach ◽  
Weak Constraints

Abstract This paper describes a new approach to an automated layout design system for industrial plant piping. The routing system, which is the main part of this layout system, is composed of three steps, according to the practical layout design process. By dividing the layout design into the optimal routing phase (Step 1, Step 2) and the arrangement phase (Step 3), it is possible to design without depending on the routing order, and with small computer memory storage capacities. The optimal route is obtained by using the routing algorithm and heuristic search, based on expert knowledge. The arrangements are made by applying the enumeration method, taking the strong and weak constraints into account.

Multicast Routing Algorithm with QoS Constraints in Mobile Ad Hoc Networks

2014 ◽  
Vol 602-605 ◽  
pp. 3169-3172 ◽  
Author(s):  
Yue Li ◽  
Yin Hui Liu ◽  
Zhong Bao Luo
Keyword(s):  
Ad Hoc ◽  
Multicast Routing ◽  
Routing Algorithm ◽  
Estimation Algorithm ◽  
Bandwidth Estimation ◽  
Routing Problem ◽  
Network Bandwidth ◽  
Hoc Networks ◽  
Multicast Routing Algorithm ◽  
Select Function

Through the study of MANET's QoS multicast routing problem, we propose a heuristic-demand multicast routing algorithm. Algorithm combines the MANET network bandwidth estimation algorithm, redefined the select function, restrictions request packets of flooding algorithm, to ensure fair treatment delay and bandwidth. Simulation results show that the algorithm has the advantage of fewer routing overhead, high success rate.

scholarly journals Reducing the Delay by Optimizing the Via in Compact Automatic Metal Routing Algorithm

2019 ◽  
Vol 8 (10) ◽  
pp. 4512-4515
Keyword(s):  
Routing Algorithm ◽  
Deep Submicron ◽  
Clock Tree ◽  
Channel Routing ◽  
Ir Drop ◽  
Clock Tree Synthesis ◽  
Tree Synthesis ◽  
Metal Layers ◽  
Synthesis Stage

The Very Deep Submicron Technology (VDSM) shrinking rapidly, we have 22nm, 14nm, 7nm and now research going on 5nm technology. That means size of the transistor shrinking, and number of interconnections increased as well. Resulting interconnections playing a major role in delay, IR drop, area etc. To reduce the delay, we are utilizing higher metal layers. Further we gone for Compact Automatic Metal Routing, nothing but Over the cell channel routing to efficiently perform routing, but the problem for such type of routing technique, stacked vias needed and that results increased resistance, delay, IR drop will degrade the performance. That may be obstacle to meet timing in Clock Tree Synthesis stage (CTS). This paper mainly focus on reducing the delay further by designing the via structure by using the tool cadence encounter

scholarly journals On the restrictive channel thickness estimation

2007 ◽  
Vol 20 (3) ◽  
pp. 499-506
Author(s):  
Iskandar Karapetyan
Keyword(s):  
Positive Integer ◽  
Heuristic Algorithms ◽  
Clique Number ◽  
Directed Path ◽  
Channel Routing ◽  
Routing Problem ◽  
Thickness Estimation ◽  
Channel Thickness ◽  
Np Complete ◽  
Routing Method

Channel routing is an important phase of physical design of LSI and VLSI chips. The channel routing method was first proposed by Akihiro Hashimoto and James Stevens [1]. The method was extensively studied by many authors and applied to different technologies. At present there are known many effective heuristic algorithms for channel routing. A. LaPaugh [2] proved that the restrictive routing problem is NP-complete. In this paper we prove that for every positive integer k there is a restrictive channel C for which ?(C)>? (HG)+L(VG)+k, where ? (C) is the thickness of the channel, ?(HG) is clique number of the horizontal constraints graph HG and L(VG) is the length of the longest directed path in the vertical constraints graph VG.

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