Evolution of IEEE 1149.1 addressable shadow protocol devices

International Test Conference, 2003. Proceedings. ITC 2003. ◽

10.1109/test.2003.1271206 ◽

2004 ◽

Cited By ~ 2

Author(s):

R.N. Joshi ◽

K.L. Williams ◽

L. Whetsel

Keyword(s):

Ieee 1149.1

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A user programmable macrocell generator for the IEEE 1149.1 boundary scan standard interface port

Microprocessing and Microprogramming ◽

10.1016/0165-6074(92)90359-f ◽

1992 ◽

Vol 35 (1-5) ◽

pp. 493-500

Author(s):

Mark Royals ◽

Tassos Markas ◽

Nick Kanopoulos

Keyword(s):

Boundary Scan ◽

Standard Interface ◽

Ieee 1149.1

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Toshiba IEEE 1149.1 (JTAG) development summary

[1991] Proceedings Fourth Annual IEEE International ASIC Conference and Exhibit ◽

10.1109/asic.1991.242915 ◽

2002 ◽

Author(s):

J. Thomas

Keyword(s):

Ieee 1149.1

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Integration of IEEE 1149.1 with mixed ECL, TTL and differential logic signals

Proceedings ETC 93 Third European Test Conference ◽

10.1109/etc.1993.246575 ◽

2002 ◽

Cited By ~ 2

Author(s):

J. Andrews

Keyword(s):

Ieee 1149.1

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An implementation of IEEE 1149.1 to avoid timing violations and other practical in-compliance improvements

Proceedings. International Test Conference ◽

10.1109/test.2002.1041827 ◽

2003 ◽

Cited By ~ 1

Author(s):

D. Stang ◽

R. Dandapani

Keyword(s):

Ieee 1149.1 ◽

Timing Violations

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An IEEE 1149.1 compliant testability architecture with internal scan

Proceedings 1992 IEEE International Conference on Computer Design: VLSI in Computers & Processors ◽

10.1109/iccd.1992.276309 ◽

2003 ◽

Cited By ~ 5

Author(s):

R.C. Zak ◽

J.V. Hill

Keyword(s):

Ieee 1149.1

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A chip to embedded system test process using IEEE 1149.1 boundary scan

Proceedings of ELECTRO '94 ◽

10.1109/electr.1994.472652 ◽

2002 ◽

Author(s):

J.E. Kadaras

Keyword(s):

Embedded System ◽

Boundary Scan ◽

Ieee 1149.1 ◽

Test Process

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Manufacturing defects testing of a multi-chip-module using IEEE 1149.1 boundary scan test and embedded built-in test software

AUTOTESTCON 93 ◽

10.1109/autest.1993.396355 ◽

2002 ◽

Author(s):

B.J. Round

Keyword(s):

Boundary Scan ◽

Manufacturing Defects ◽

Scan Test ◽

Ieee 1149.1 ◽

Boundary Scan Test

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An IEEE 1149.1 based voltmeter/oscilloscope in a chip

Digest of Papers Eleventh Annual 1993 IEEE VLSI Test Symposium ◽

10.1109/vtest.1993.313310 ◽

2002 ◽

Cited By ~ 7

Author(s):

L. Whetsel

Keyword(s):

Ieee 1149.1

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Optimal placement of IEEE 1149.1 test port and boundary scan resources for wafer scale integration

Proceedings. International Test Conference 1990 ◽

10.1109/test.1990.114009 ◽

2002 ◽

Cited By ~ 3

Author(s):

D.L. Landis ◽

P. Singh

Keyword(s):

Optimal Placement ◽

Boundary Scan ◽

Wafer Scale ◽

Wafer Scale Integration ◽

Ieee 1149.1 ◽

Scale Integration

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An IEEE 1149.1 based test access architecture for ICs with embedded cores

Proceedings International Test Conference 1997 ◽

10.1109/test.1997.639596 ◽

2002 ◽

Cited By ~ 65

Author(s):

L. Whetsel

Keyword(s):

Embedded Cores ◽

Ieee 1149.1

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