A comparison of bridging fault simulation methods

2003 ◽  
Author(s):  
S. Ma ◽  
I. Shaik ◽  
R.S. Fetherston
Keyword(s):  
Fault Simulation ◽  
Simulation Methods ◽  
Bridging Fault

Fault-Simulation Methods-Extensions and Comparison

1981 ◽  
Vol 60 (9) ◽  
pp. 2235-2258 ◽  
Author(s):  
Y. H. Levendel ◽  
P. R. Menon
Keyword(s):  
Fault Simulation ◽  
Simulation Methods

Resistive bridging fault simulation of industrial circuits

2008 ◽  
Author(s):  
Piet Engelke ◽  
Ilia Polian ◽  
Juergen Schloeffel ◽  
Bernd Becker
Keyword(s):  
Fault Simulation ◽  
Bridging Fault ◽  
Industrial Circuits

Resistive Bridging Fault Simulation of Industrial Circuits

2008 ◽  
Author(s):  
Piet Engelke ◽  
Ilia Polian ◽  
Juergen Schloeffel ◽  
Bernd Becker
Keyword(s):  
Fault Simulation ◽  
Bridging Fault ◽  
Industrial Circuits

scholarly journals Design of OBD function test on production vehicle (PVE)

2021 ◽  
Vol 268 ◽  
pp. 01047
Author(s):  
Lihui Wang ◽  
Xionghui Zou ◽  
Hongyu Qin ◽  
Peilin Geng
Keyword(s):  
Fault Simulation ◽  
Technical Skills ◽  
Simulation Method ◽  
Test Methods ◽  
Simulation Methods ◽  
Test Procedures ◽  
Test Specifications ◽  
Function Test ◽  
Late Start ◽  
Failure Monitoring

Production Vehicle Evaluation (PVE) test mainly verifies the functionality of OBD system. PVE J2 test needs to verify the diagnostic mechanism for all the diagnostic Trouble Codes (DTC). While the design of fault simulation method is one of the technical difficulties of the whole PVE test. Due to the late start of PVE in China, test methods and technical skills are inadequate. This paper elaborates the failure monitoring principle and diagnosis mechanism of OBD system in detail,systematically introduces the PVE methods and J1, J2, J3 test procedures, studies and analyses the types of OBD malfunction and various fault simulation methods,finally forms a set of PVE test specifications.

Comparison of Parallel and Deductive Fault Simulation Methods

1974 ◽  
Vol C-23 (11) ◽  
pp. 1132-1138 ◽  
Author(s):  
H.Y.-P. Chang ◽  
S.G. Chappell ◽  
C.H. Elmendorf ◽  
L.D. Schmidt
Keyword(s):  
Fault Simulation ◽  
Simulation Methods

scholarly journals Defect-oriented mixed-level fault simulation in digital systems

2002 ◽  
Vol 15 (1) ◽  
pp. 123-136
Author(s):  
Raimund Ubar ◽  
Jaan Raik ◽  
Eero Ivask ◽  
Marina Brik
Keyword(s):  
Fault Simulation ◽  
Register Transfer Level ◽  
Digital Systems ◽  
Decision Diagrams ◽  
Simulation Methods ◽  
Test Quality ◽  
Quality Estimation ◽  
Uniform Model ◽  
Physical Defects ◽  
Logic Level

A new method for mixed level defect-oriented fault simulation of Digital Systems represented with Decision Diagrams (DD) is proposed. We suppose that a register transfer level (RTL) information along with gate-level descriptions for RTL blocks are available. Decision diagrams (DDs) are exploited as a uniform model for describing circuits on both levels. The physical defects in the system are mapped to the logic level and are simulated on the mixed gate- and RT levels. The approach proposed allows to increase the accuracy of test quality estimation, and to reduce simulation cost in comparison to traditional gate-level fault simulation methods.

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