Internet of Things (IOT) Based Smart Switch

As the years progress, our world is becoming more technologically advanced, and humanity will soon be technologically focused. Henceforth, some fundamental measures should be made by individuals in order to develop the advanced next generation technologies. In this perspective, the proposed research work has developed an Android application with a unit comprising of ESP8266 Wi-Fi module, relay, logic level converter module, capacitive touch sensor module and also a Wi-Fi technology has been used to control the switches.

Improving Characteristics of LUT-Based Mealy FSMs with Twofold State Assignment

Practically, any digital system includes sequential blocks. This article is devoted to a case when sequential blocks are represented by models of Mealy finite state machines (FSMs). The performance (maximum operating frequency) is one of the most important characteristics of an FSM circuit. In this article, a method is proposed which aims at increasing the operating frequency of LUT-based Mealy FSMs with twofold state assignment. This is done using only extended state codes. Such an approach allows excluding a block of transformation of binary state codes into extended state codes. The proposed approach leads to LUT-based Mealy FSM circuits having two levels of logic blocks. Each function for any logic level is represented by a circuit including a single LUT. The proposed method is illustrated by an example of synthesis. The results of experiments conducted with standard benchmarks show that the proposed approach produces LUT-based circuits with significantly higher operating frequency than it is for circuits produced by other investigated methods (Auto and One-hot of Vivado, JEDI, twofold state assignment). The performance is increased by an average of 15.9 to 25.49 percent. These improvements are accompanied by a small growth of the numbers of LUTs compared with circuits based on twofold state assignment. Our approach provides the best area-time products compared with other investigated methods. The advantages of the proposed approach increase as the number of FSM inputs and states increases.

Monolithic Integrated High Frequency GaN DC-DC Buck Converters with High Power Density Controlled by Current Mode Logic Level Signal

Integration is a key way to improve the switching frequency and power density for a DC-DC converter. A monolithic integrated GaN based DC-DC buck converter is realized by using a gate driver and a half-bridge power stage. The gate driver is composed of three stages (amplitude amplifier stage, level shifting stage and resistive-load amplifier stage) to amplify and modulate the driver control signal, i.e., CML (current mode logic) level of which the swing is from 1.1 to 1.8 V meaning that there is no need for an additional buffer or preamplifier for the control signal. The gate driver can provide sufficient driving capability for the power stage and improve the power density efficiently. The proposed GaN based DC-DC buck converter is implemented in the 0.25 μm depletion mode GaN-on-SiC process with a chip area of 1.7 mm × 1.3 mm, which is capable of operating at high switching frequency up to 200 MHz and possesses high power density up to 1 W/mm2 at 15 V output voltage. To the authors’ knowledge, this is the highest power density for GaN based DC-DC converter at the hundreds of megahertz range.

High-Performance SIP Half-Bridge IPM Based on 35mΩ/1200V SiC Stack-Cascode

A SiC-based high-performance Intelligent Power Modules (IPM) was developed. It is a System In Package (SIP) module that consist of a half-bridge with driver. In the developed SIP IPM, the internal half-bridge is made up of UnitedSiC 35mΩ/1200V Stack-Cascode switches (UF3SC120035Z) which have low on-resistance, low gate charge, simple gate drive of VGS=0 or-5V to VGS=12V, excellent integral body diode and very low switching losses. The module operates with control voltage of 12-15V for both the low and high side switches, and a logic level input that can be 3.3V, 5V or 12V. We believe that this module will enable extremely efficient switching up to 250-400kHz, depending on topology, offering several hundred kHz even in hard-switched applications.

Interfacing TTL and CMOS Logic Levels in the Laboratory

ABSTRACT Interconnectivity of electrical components, such as triggers and detectors, is intrinsic to operating time-sensitive experiments. As labs become more digitized, equipment integration and compatibility become larger factors in experimental setups. Complications can arise when instruments with different signal levels, or logic levels, are integrated because each instrument requires its own particular input signal, with a specific threshold voltage, to function. When incorrect logic levels are used or the delays in conversion are too long, these instruments are not properly triggered and the experiment becomes inoperable. To perform multi-component, time-sensitive experiments, a logic-level converter with minimal time delays is necessary. Commercial solutions, however, are not viable when the nature of the experiment is highly time-sensitive, such as in laser spectroscopy, because the delay on the signal conversion is several hundred nanoseconds and would result in missed events. In this paper, three different logic-level converter circuits are presented for conversion between the TTL and CMOS logic levels, the most commonly used logic levels in experimental applications, based on the concept of an emitter follower design that only produces a delay in the tens of nanoseconds. Circuits were developed for conversion from CMOS to TTL, from TTL to CMOS, and a TTL buffer circuit. These circuits allow for inter-conversion between the two most common logic families, TTL and CMOS, as well as buffering weak signals, to offer a simple, low-cost solution to synchronization in time-sensitive experimental setups.