An almost full-scan BIST solution-higher fault coverage and shorter test application time

2002 ◽  
Author(s):  
Huan-Chih Tsai ◽  
S. Bhawmik ◽  
Kwane-Ting Cheng
Keyword(s):  
Fault Coverage ◽  
Application Time ◽  
Test Application Time ◽  
Test Application ◽  
Full Scan

scholarly journals MULTI-DEGREE SMOOTHER FOR LOW POWER TESTABLE DIGITAL SYSTEM DESIGN USING BS-LFSR AND SCAN-CHAIN ORDERING TECHNIQUES

2014 ◽  
pp. 23-30
Author(s):  
V. SURYANARAYANA ◽  
K. MIRANJI
Keyword(s):  
Peak Power ◽  
Average Power ◽  
Fault Coverage ◽  
Experimental Results ◽  
Application Time ◽  
Test Application Time ◽  
Test Application ◽  
Average Power Consumption ◽  
Scan Chain ◽  
Chain Ordering

Testing of digital VLSI circuits entails many challenges as a consequence of rapid growth of semiconductor manufacturing technology and the unprecedented levels of design complexity and the gigahertz range of operating frequencies. These challenges include keeping the average and peak power dissipation and test application time within acceptable limits. This dissertation proposes techniques to addresses these challenges during test. The first proposed technique, called bit-swapping LFSR (BS-LFSR), uses new observations concerning the output sequence of an LFSR to design a low-transition test-pattern-generator (TPG) for test-per-clock built-in self-test (BIST) to achieve reduction in the overall switching activity in the circuit-under-test (CUT). The obtained results show up to 28% power reduction for the proposed design, and up-to 63% when it is combined with another established technique. The proposed BS-LFSR is then extended for use in test-per-scantest vectors show up to 60%reduction in average power consumption. The BS-LFSR is then extended further to act as a multi-degree smoother for test patterns generated by conventional LFSRs before applying them to the CUT. Experimental results show up to 55% reduction in average power. Another technique that aims to reduce peak power in scan-based BIST is presented. The new technique uses a two-phase scan-chain ordering algorithm to reduce average and peak power in scan and capture cycles. Experimental results show up to 65% and 55% reduction in average and peak power, respectively. Finally, a technique that aims to significantly increase the fault coverage in test-Per scan BIST, while keeping the test-application time short, is proposed. The results obtained show a significant improvement in fault coverage and test application time compared with other techniques.

scholarly journals Partial Reset: An Alternative DFT Approach

VLSI Design ◽  
1994 ◽  
Vol 1 (4) ◽  
pp. 299-311 ◽  
Author(s):  
Ben Mathew ◽  
Daniel G. Saab
Keyword(s):  
Dft Method ◽  
Design For Testability ◽  
Application Time ◽  
High Coverage ◽  
Partial Scan ◽  
Test Application Time ◽  
Test Application ◽  
Full Scan ◽  
The Many ◽  
Partial Reset

Design for testability (DFT) techniques reduce testing costs at the price of extra hardware. Among the many DFT techniques that have been proposed for this task are full scan, partial scan and hardware reset. In this paper we explore a relatively new DFT method, called partial reset. Reset lines are added to only a subset of the flip-flops and obtain reasonably high coverage. This approach has lower overhead in terms of test application time and hardware area when compared to previous ones. Further enhancement of the controllability is obtained by using multiple reset lines. The configuration of these multiple reset lines is described. This technique has been evaluated on the 1989 ISCAS sequential benchmark circuits and obtained favorable results.

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