A novel scheme to reduce test application time in circuits with full scan

1995 ◽  
Vol 14 (12) ◽  
pp. 1577-1586 ◽  
Author(s):  
D.K. Pradhan ◽  
J. Saxena
Keyword(s):  
Application Time ◽  
Test Application Time ◽  
Test Application ◽  
Full Scan

scholarly journals Partial Reset: An Alternative DFT Approach

VLSI Design ◽  
1994 ◽  
Vol 1 (4) ◽  
pp. 299-311 ◽  
Author(s):  
Ben Mathew ◽  
Daniel G. Saab
Keyword(s):  
Dft Method ◽  
Design For Testability ◽  
Application Time ◽  
High Coverage ◽  
Partial Scan ◽  
Test Application Time ◽  
Test Application ◽  
Full Scan ◽  
The Many ◽  
Partial Reset

Design for testability (DFT) techniques reduce testing costs at the price of extra hardware. Among the many DFT techniques that have been proposed for this task are full scan, partial scan and hardware reset. In this paper we explore a relatively new DFT method, called partial reset. Reset lines are added to only a subset of the flip-flops and obtain reasonably high coverage. This approach has lower overhead in terms of test application time and hardware area when compared to previous ones. Further enhancement of the controllability is obtained by using multiple reset lines. The configuration of these multiple reset lines is described. This technique has been evaluated on the 1989 ISCAS sequential benchmark circuits and obtained favorable results.

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