Effective path selection for delay fault testing of sequential circuits

Proceedings International Test Conference 1997 ◽

10.1109/test.1997.639716 ◽

2002 ◽

Cited By ~ 14

Author(s):

T.J. Chakraborty ◽

V.D. Agrawal

Keyword(s):

Path Selection ◽

Sequential Circuits ◽

Fault Testing ◽

Delay Fault ◽

Delay Fault Testing ◽

Selection For ◽

Effective Path

Download Full-text

On path selection for delay fault testing considering operating conditions [logic IC testing]

The Eighth IEEE European Test Workshop, 2003. Proceedings. ◽

10.1109/etw.2003.1231681 ◽

2004 ◽

Cited By ~ 8

Author(s):

B. Seshadri ◽

I. Pomeranz ◽

S.M. Reddy ◽

S. Kundu

Keyword(s):

Path Selection ◽

Operating Conditions ◽

Fault Testing ◽

Delay Fault ◽

Delay Fault Testing ◽

Selection For ◽

Ic Testing

Download Full-text

Parameterized Critical Path Selection for Delay Fault Testing

2015 IEEE 18th International Symposium on Design and Diagnostics of Electronic Circuits & Systems ◽

10.1109/ddecs.2015.62 ◽

2015 ◽

Cited By ~ 1

Author(s):

Miroslav Siebert ◽

Elena Gramatova

Keyword(s):

Critical Path ◽

Path Selection ◽

Fault Testing ◽

Delay Fault ◽

Delay Fault Testing ◽

Selection For ◽

Critical Path Selection

Download Full-text

Recursive Path Selection for Delay Fault Testing

2009 27th IEEE VLSI Test Symposium ◽

10.1109/vts.2009.50 ◽

2009 ◽

Cited By ~ 4

Author(s):

Jaeyong Chung ◽

Jacob A. Abraham

Keyword(s):

Path Selection ◽

Fault Testing ◽

Delay Fault ◽

Delay Fault Testing ◽

Selection For ◽

Recursive Path

Download Full-text

On theoretical and practical considerations of path selection for delay fault testing

IEEE/ACM International Conference on Computer Aided Design, 2002. ICCAD 2002. ◽

10.1145/774572.774586 ◽

2002 ◽

Cited By ~ 1

Author(s):

Jing-Jia Liou ◽

Li-C. Wang ◽

Kwang-Ting Cheng

Keyword(s):

Path Selection ◽

Fault Testing ◽

Delay Fault ◽

Delay Fault Testing ◽

Selection For

Download Full-text

On theoretical and practical considerations of path selection for delay fault testing

IEEE/ACM International Conference on Computer Aided Design, 2002. ICCAD 2002. ◽

10.1109/iccad.2002.1167519 ◽

2003 ◽

Cited By ~ 14

Author(s):

Jing-Jia Liou ◽

L.-C. Wang ◽

Kwang-Ting Cheng

Keyword(s):

Path Selection ◽

Fault Testing ◽

Delay Fault ◽

Delay Fault Testing ◽

Selection For

Download Full-text

Critical Path Selection for Delay Fault Testing Based Upon a Statistical Timing Model

IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems ◽

10.1109/tcad.2004.835137 ◽

2004 ◽

Vol 23 (11) ◽

pp. 1550-1565 ◽

Cited By ~ 75

Author(s):

L.-C. Wang ◽

J.-J. Liou ◽

K.-T. Cheng

Keyword(s):

Critical Path ◽

Path Selection ◽

Fault Testing ◽

Delay Fault ◽

Delay Fault Testing ◽

Timing Model ◽

Selection For ◽

Statistical Timing ◽

Critical Path Selection

Download Full-text

A flexible path selection procedure for path delay fault testing

Proceedings 17th IEEE VLSI Test Symposium (Cat. No.PR00146) ◽

10.1109/vtest.1999.766659 ◽

2003 ◽

Cited By ~ 5

Author(s):

I. Pomeranz ◽

S.M. Reddy

Keyword(s):

Selection Procedure ◽

Path Selection ◽

Path Delay ◽

Fault Testing ◽

Delay Fault ◽

Delay Fault Testing ◽

Path Delay Fault ◽

Path Delay Fault Testing

Download Full-text

Flip-flop sharing in standard scan path to enhance delay fault testing of sequential circuits

Proceedings of the Fourth Asian Test Symposium ◽

10.1109/ats.1995.485359 ◽

2002 ◽

Cited By ~ 12

Author(s):

J.P. Hurst ◽

N. Kanopoulos

Keyword(s):

Sequential Circuits ◽

Fault Testing ◽

Delay Fault ◽

Flip Flop ◽

Delay Fault Testing ◽

Scan Path

Download Full-text

Power Supply Voltage Control for Eliminating Overkills and Underkills in Delay Fault Testing

IEICE Transactions on Electronics ◽

10.1587/transele.e99.c.1219 ◽

2016 ◽

Vol E99.C (10) ◽

pp. 1219-1225

Author(s):

Masahiro ISHIDA ◽

Toru NAKURA ◽

Takashi KUSAKA ◽

Satoshi KOMATSU ◽

Kunihiro ASADA

Keyword(s):

Power Supply ◽

Supply Voltage ◽

Voltage Control ◽

Fault Testing ◽

Power Supply Voltage ◽

Delay Fault ◽

Delay Fault Testing

Download Full-text

Power Supply Noise-Aware Scan Test Pattern Reshaping for At-Speed Delay Fault Testing of Monolithic 3D ICs *

2020 IEEE 29th Asian Test Symposium (ATS) ◽

10.1109/ats49688.2020.9301568 ◽

2020 ◽

Author(s):

Shao-Chun Hung ◽

Yi-Chen Lu ◽

Sung Kyu Lim ◽

Krishnendu Chakrabarty

Keyword(s):

Power Supply ◽

Test Pattern ◽

Power Supply Noise ◽

Fault Testing ◽

Delay Fault ◽

Delay Fault Testing ◽

3D Ics ◽

Scan Test ◽

Supply Noise

Download Full-text