A built-in self-test circuit with timing margin test function in a 1 Gbit synchronous DRAM

Author(s):  
N. Sakashita ◽  
F. Okuda ◽  
K. Shimomura ◽  
H. Shimano ◽  
M. Hamada ◽  
...  
2013 ◽  
Vol 34 (12) ◽  
pp. 125007
Author(s):  
Lei Zhou ◽  
Danyu Wu ◽  
Fan Jiang ◽  
Zhi Jin ◽  
Xinyu Liu

2013 ◽  
Vol 7 (6) ◽  
pp. 181-190 ◽  
Author(s):  
Woo-Chang Choi ◽  
Jee-Youl Ryu ◽  
Sookyoung Joung

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