A Compression Improvement Technique for Low-Power Scan Test Data

2006 ◽  
Author(s):  
Jaehoon Song ◽  
Hyunbean Yi ◽  
Doochan Hwang ◽  
Sungju Park
Keyword(s):  
Low Power ◽  
Test Data ◽  
Scan Test

An integrated DFT solution for power reduction in scan test applications by low power gating scan cell

Integration ◽  
2017 ◽  
Vol 57 ◽  
pp. 108-124 ◽  
Author(s):  
Mahshid Mojtabavi Naeini ◽  
Sreedharan Baskara Dass ◽  
Chia Yee Ooi ◽  
Tomokazu Yoneda ◽  
Michiko Inoue
Keyword(s):  
Low Power ◽  
Power Reduction ◽  
Power Gating ◽  
Scan Test

Efficient Low-power Scan Test Method based on Exclusive Scan and Scan Chain Reordering

2020 ◽  
Vol 20 (4) ◽  
pp. 390-404
Author(s):  
Dooyoung Kim ◽  
Jinuk Kim ◽  
Muhammad Ibtesam ◽  
Umair Saeed Solangi ◽  
Sungju Park
Keyword(s):  
Low Power ◽  
Test Method ◽  
Scan Test ◽  
Scan Chain

Design Techniques with Multiple Scan Compression CoDecs for Low Power and High Quality Scan Test

2011 ◽  
Vol 7 (4) ◽  
pp. 502-515 ◽  
Author(s):  
Arvind Jain ◽  
Sundarrajan Subramanian ◽  
Rubin A. Parekhji ◽  
Srivaths Ravi
Keyword(s):  
Low Power ◽  
High Quality ◽  
Scan Test ◽  
Multiple Scan ◽  
Design Techniques

scholarly journals Scan Chain Ordering to Reduce Test Data for BIST-Aided Scan Test Using Compatible Scan Flip-Flops

2010 ◽  
Vol E93-D (1) ◽  
pp. 10-16 ◽  
Author(s):  
Hiroyuki YOTSUYANAGI ◽  
Masayuki YAMAMOTO ◽  
Masaki HASHIZUME
Keyword(s):  
Test Data ◽  
Scan Test ◽  
Scan Chain ◽  
Chain Ordering

Low-Power Hierarchical Scan Test for Multiple Clock Domains

2007 ◽  
Vol 3 (1) ◽  
pp. 106-118 ◽  
Author(s):  
T. Senthil Arasu ◽  
C. P. Ravikumar ◽  
S. K. Nandy
Keyword(s):  
Low Power ◽  
Scan Test ◽  
Clock Domains
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