scholarly journals Analyzing the Effect of High-k Dielectric-Mediated Doping on Contact Resistance in Top-Gated Monolayer MoS2 Transistors

2018 ◽  
Vol 65 (10) ◽  
pp. 4084-4092 ◽  
Author(s):  
Abdullah Alharbi ◽  
Davood Shahrjerdi
Keyword(s):  
Contact Resistance ◽  
Monolayer Mos2 ◽  
High K ◽  
High K Dielectric

Effects of high-k dielectric environment on the full ballistic transport properties of monolayer MoS2 FETs

2017 ◽  
Vol 121 (14) ◽  
pp. 144505 ◽  
Author(s):  
Xian-Jiang Song ◽  
Li-Chun Xu ◽  
Hui-Fang Bai ◽  
Ying Li ◽  
Zhiyuan Ma ◽  
...  
Keyword(s):  
Transport Properties ◽  
Ballistic Transport ◽  
Monolayer Mos2 ◽  
High K ◽  
High K Dielectric ◽  
Dielectric Environment

scholarly journals Impact and Origin of Interface States in MOS Capacitor with Monolayer MoS2 and HfO2 High-k Dielectric

2017 ◽  
Vol 7 (1) ◽  
Author(s):  
Pengkun Xia ◽  
Xuewei Feng ◽  
Rui Jie Ng ◽  
Shijie Wang ◽  
Dongzhi Chi ◽  
...  
Keyword(s):  
Interface States ◽  
Monolayer Mos2 ◽  
Mos Capacitor ◽  
High K ◽  
High K Dielectric

Sub-20nm Device Voltage-Sensitive SRAM Characterization and Failure Analysis

2018 ◽  
Author(s):  
Seng Nguon Ting ◽  
Hsien-Ching Lo ◽  
Donald Nedeau ◽  
Aaron Sinnott ◽  
Felix Beaudoin
Keyword(s):  
Failure Analysis ◽  
High Performance ◽  
Yield Loss ◽  
Technology Development ◽  
High Density ◽  
High K ◽  
Yield Learning ◽  
Oxide Deposition ◽  
Edge Profile ◽  
High K Dielectric

Abstract With rapid scaling of semiconductor devices, new and more complicated challenges emerge as technology development progresses. In SRAM yield learning vehicles, it is becoming increasingly difficult to differentiate the voltage-sensitive SRAM yield loss from the expected hard bit-cells failures. It can only be accomplished by extensively leveraging yield, layout analysis and fault localization in sub-micron devices. In this paper, we describe the successful debugging of the yield gap observed between the High Density and the High Performance bit-cells. The SRAM yield loss is observed to be strongly modulated by different active sizing between two pull up (PU) bit-cells. Failure analysis focused at the weak point vicinity successfully identified abnormal poly edge profile with systematic High k Dielectric shorts. Tight active space on High Density cells led to limitation of complete trench gap-fill creating void filled with gate material. Thanks to this knowledge, the process was optimized with “Skip Active Atomic Level Oxide Deposition” step improving trench gap-fill margin.

A Substitution for the High- k Dielectric in an AlGaN/GaN Metal-insulator-Semiconductor Heterostructure

2012 ◽  
Vol 29 (5) ◽  
pp. 057702 ◽  
Author(s):  
Yue-Chan Kong ◽  
Fang-Shi Xue ◽  
Jian-Jun Zhou ◽  
Liang Li ◽  
Chen Chen ◽  
...  
Keyword(s):  
Metal Insulator ◽  
Metal Insulator Semiconductor ◽  
Semiconductor Heterostructure ◽  
High K ◽  
High K Dielectric

Polysilicon Nanowire Sensor Devices Based on High-k Dielectric Membrane for pH Sensing and DNA Detection

2012 ◽  
Vol 45 (3) ◽  
pp. 537-542 ◽  
Author(s):  
C.-Y. Wu ◽  
P.-Y. Hsu ◽  
C. L. Wang ◽  
T.-C. Liao ◽  
H.-C. Cheng ◽  
...  
Keyword(s):  
Dna Detection ◽  
Ph Sensing ◽  
High K ◽  
Sensor Devices ◽  
Nanowire Sensor ◽  
High K Dielectric
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