2-D Analytical Drain Current Model of Double-Gate Heterojunction TFETs With a SiO2/HfO2 Stacked Gate-Oxide Structure

Sanjay Kumar; Kunal Singh; Sweta Chander; Ekta Goel; Prince Kumar Singh; Kamalaksha Baral; Balraj Singh; Satyabrata Jit

doi:10.1109/ted.2017.2773560

2-D Analytical Drain Current Model of Double-Gate Heterojunction TFETs With a SiO2/HfO2 Stacked Gate-Oxide Structure

IEEE Transactions on Electron Devices ◽

10.1109/ted.2017.2773560 ◽

2018 ◽

Vol 65 (1) ◽

pp. 331-338 ◽

Cited By ~ 31

Author(s):

Sanjay Kumar ◽

Kunal Singh ◽

Sweta Chander ◽

Ekta Goel ◽

Prince Kumar Singh ◽

...

Keyword(s):

Current Model ◽

Drain Current ◽

Gate Oxide ◽

Double Gate ◽

Oxide Structure

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Analytical drain current model using temperature dependence model in nanoscale Double-Gate (DG) MOSFETs

2013 14th International Conference on Ultimate Integration on Silicon (ULIS) ◽

10.1109/ulis.2013.6523503 ◽

2013 ◽

Cited By ~ 1

Author(s):

M. Cheralathan ◽

C. Sampedro ◽

F. Gamiz ◽

B. Iniguez

Keyword(s):

Temperature Dependence ◽

Current Model ◽

Drain Current ◽

Double Gate

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An analytical charge-based drain current model for nano-scale In0.52Al0.48As–In0.53Ga0.47as a separated double-gate HEMT

Semiconductor Science and Technology ◽

10.1088/0268-1242/25/11/115003 ◽

2010 ◽

Vol 25 (11) ◽

pp. 115003 ◽

Cited By ~ 1

Author(s):

Servin Rathi ◽

Jyotika Jogi ◽

Mridula Gupta ◽

R S Gupta

Keyword(s):

Current Model ◽

Drain Current ◽

Double Gate ◽

Nano Scale

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An Accurate Drain Current Model of Dual Material Double Gate Metal Oxide Semiconductor Field Effect Transistor

Silicon ◽

10.1007/s12633-021-01321-y ◽

2021 ◽

Author(s):

Himeli Chakrabarti ◽

Reshmi Maity ◽

S. Baishya ◽

N. P. Maity

Keyword(s):

Metal Oxide ◽

Field Effect ◽

Field Effect Transistor ◽

Current Model ◽

Drain Current ◽

Metal Oxide Semiconductor ◽

Oxide Semiconductor ◽

Double Gate ◽

Effect Transistor ◽

Dual Material

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Analytical drain current model to study the impact of interface trap charges on device performance of Double Gate Ge Ferroelectric FET (DGGeFeFET)

2018 Conference on Emerging Devices and Smart Systems (ICEDSS) ◽

10.1109/icedss.2018.8544314 ◽

2018 ◽

Author(s):

Monika Bansal ◽

Harsupreet Kaur

Keyword(s):

Current Model ◽

Drain Current ◽

Interface Trap ◽

Device Performance ◽

Double Gate ◽

The Impact ◽

Trap Charges

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A unified drain current model for nanoscale double-gate and surrounding-gate MOSFETs incorporating velocity saturation

2010 3rd International Nanoelectronics Conference (INEC) ◽

10.1109/inec.2010.5424994 ◽

2010 ◽

Author(s):

Lining Zhang ◽

Xingye Zhou ◽

Yiwen Xu ◽

Lin Chen ◽

Wang Zhou ◽

...

Keyword(s):

Current Model ◽

Drain Current ◽

Double Gate ◽

Velocity Saturation ◽

Surrounding Gate

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Drain current model for double-gate tunnel field-effect transistor with hetero-gate-dielectric and source-pocket

Microelectronics Reliability ◽

10.1016/j.microrel.2015.09.014 ◽

2016 ◽

Vol 59 ◽

pp. 30-36 ◽

Cited By ~ 7

Author(s):

Ping Wang ◽

YiQi Zhuang ◽

Cong Li ◽

Zhi Jiang ◽

YuQi Liu

Keyword(s):

Field Effect ◽

Field Effect Transistor ◽

Gate Dielectric ◽

Current Model ◽

Drain Current ◽

Double Gate ◽

Effect Transistor ◽

Tunnel Field Effect Transistor

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2-D Analytical Modeling of the Electrical Characteristics of Dual-Material Double-Gate TFETs With a SiO2/HfO2 Stacked Gate-Oxide Structure

IEEE Transactions on Electron Devices ◽

10.1109/ted.2017.2656630 ◽

2017 ◽

Vol 64 (3) ◽

pp. 960-968 ◽

Cited By ~ 72

Author(s):

Sanjay Kumar ◽

Ekta Goel ◽

Kunal Singh ◽

Balraj Singh ◽

Prince Kumar Singh ◽

...

Keyword(s):

Analytical Modeling ◽

Gate Oxide ◽

Double Gate ◽

Electrical Characteristics ◽

Oxide Structure ◽

Dual Material

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Enhancement and Modeling of Drain Current in Negative Capacitance Double Gate TFET

10.21203/rs.3.rs-271741/v1 ◽

2021 ◽

Author(s):

SHIKHA U S ◽

Rekha K James ◽

Jobymol Jacob ◽

Anju Pradeep

Keyword(s):

Drain Current ◽

Gate Oxide ◽

Negative Capacitance ◽

Double Gate ◽

High K ◽

Gate Control ◽

Effect Transistor ◽

Dimensional Simulation ◽

The Impact ◽

Low K

Abstract The drain current improvement in a Negative Capacitance Double Gate Tunnel Field Effect Transistor (NC-DG TFET) with the help of Heterojunction (HJ) at the source-channel region is proposed and modeled in this paper. The gate oxide of the proposed TFET is a stacked configuration of high-k over low-k to improve the gate control without any lattice mismatches. Tangent Line Approximation (TLA) method is used here to model the drain current accurately. The model is validated by incorporating two dimensional simulation of DG-HJ TFET with one dimensional Landau-Khalatnikov (LK) equation. The model matches excellently with the device simulation results. The impact of stacked gate oxide topology is also studied in this paper by comparing the characteristics with unstacked gate oxide. Voltage amplification factor (Av), which is an important parameter in NC devices is also analyzed.

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