Drain current model for double-gate tunnel field-effect transistor with hetero-gate-dielectric and source-pocket

2016 ◽  
Vol 59 ◽  
pp. 30-36 ◽  
Author(s):  
Ping Wang ◽  
YiQi Zhuang ◽  
Cong Li ◽  
Zhi Jiang ◽  
YuQi Liu
Keyword(s):  
Field Effect ◽  
Field Effect Transistor ◽  
Gate Dielectric ◽  
Current Model ◽  
Drain Current ◽  
Double Gate ◽  
Effect Transistor ◽  
Tunnel Field Effect Transistor

scholarly journals Drain Current Model for a Single Gate Tunnel Field Effect Transistor with Hetero-Dielectric Gate (HDG)

2021 ◽  
Author(s):  
AJAY Kumar SINGH ◽  
Tan Chun Fui ◽  
Lim Way Soong
Keyword(s):  
Closed Form ◽  
Field Effect ◽  
Field Effect Transistor ◽  
Current Model ◽  
Tunneling Current ◽  
Drain Current ◽  
Analytical Models ◽  
Potential Candidate ◽  
Effect Transistor ◽  
Tunnel Field Effect Transistor

Abstract Purpose: A TFET (Tunnel Field Effect Transistor) is a potential candidate to replace CMOS in deep-submicron region due to its lower SS (subthreshold swing, <60 mV/decade) at room temperature. However, the conventional TFET suffers from low tunneling current and high ambipolar current. To overcome these two drawbacks a new structure, known as Hetero-dielectric gate TFET (HDG TFET), has been proposed in the literature. Method: To analyze the electrical characteristics of this structure, a closed form of analytical expression of current is required. This paper presents the closed form of compact analytical current model for HDG TFET structure without using any iterative method. Result: The developed compact analytical models show a good agreement with 2-D TCAD simulator results. The model is used to study in depth about the electrical behavior of the device under various physical variation as well as bias variation. Conclusion: The proposed model can be incorporated into SPICE to describe the behavior of HDG TFET faster.

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