Compact Modeling of Surface Potential, Charge, and Current in Nanoscale Transistors Under Quasi-Ballistic Regime

2016 ◽  
Vol 63 (11) ◽  
pp. 4151-4159 ◽  
Author(s):  
Avirup Dasgupta ◽  
Amit Agarwal ◽  
Sourabh Khandelwal ◽  
Yogesh Singh Chauhan
Keyword(s):  
Surface Potential ◽  
Compact Modeling ◽  
Ballistic Regime ◽  
Nanoscale Transistors

Compact Modeling of Surface Potential and Drain Current in Multi-layered MoS2 FETs

2020 ◽  
Author(s):  
Keshari Nandan ◽  
Chandan Yadav ◽  
Priyank Rastogi ◽  
Alejandro Toral-Lopez ◽  
Antonio Marin-Sanchez ◽  
...  
Keyword(s):  
Surface Potential ◽  
Drain Current ◽  
Compact Modeling ◽  
Layered Mos2

Surface-potential-based compact modeling of dynamically depleted SOI MOSFETs

2010 ◽  
Vol 54 (5) ◽  
pp. 595-604 ◽  
Author(s):  
Weimin Wu ◽  
Wei Yao ◽  
Gennady Gildenblat
Keyword(s):  
Surface Potential ◽  
Compact Modeling

scholarly journals Surface-Potential-Based Compact Modeling of p-GaN Gate HEMTs

Micromachines ◽  
2021 ◽  
Vol 12 (2) ◽  
pp. 199
Author(s):  
Jie Wang ◽  
Zhanfei Chen ◽  
Shuzhen You ◽  
Benoit Bakeroot ◽  
Jun Liu ◽  
...  
Keyword(s):  
Surface Potential ◽  
High Electron Mobility Transistors ◽  
Compact Modeling ◽  
Physical Parameters ◽  
High Electron ◽  
Doping Density ◽  
Electron Mobility Transistors ◽  
The Poisson Equation ◽  
Proposed Model ◽  
High Degree

We propose a surface potential (SP)-based compact model of p-GaN gate high electron mobility transistors (HEMTs) which solves the Poisson equation. The model includes all possible charges in the GaN channel layer, including the unintended Mg doping density caused by out-diffusion. The SP equation and its analytical approximate solution provide a high degree of accuracy for the SP calculation, from which the closed-form I–V equations are derived. The proposed model uses physical parameters only and is implemented in Verilog-A code.

Surface-Potential-Based Compact Modeling of Gate Current in AlGaN/GaN HEMTs

2015 ◽  
Vol 62 (2) ◽  
pp. 443-448 ◽  
Author(s):  
Sudip Ghosh ◽  
Avirup Dasgupta ◽  
Sourabh Khandelwal ◽  
Shantanu Agnihotri ◽  
Yogesh Singh Chauhan
Keyword(s):  
Surface Potential ◽  
Compact Modeling ◽  
Gate Current ◽  
Gan Hemts

scholarly journals A physically based relation between extracted threshold voltage and surface potential flat band voltage for MOSFET compact modeling

2001 ◽  
Vol 48 (5) ◽  
pp. 1019-1021 ◽  
Author(s):  
J. Benson ◽  
N.V. D'Halleweyn ◽  
W. Redman-White ◽  
C.A. Easson ◽  
M.J. Uren ◽  
...  
Keyword(s):  
Surface Potential ◽  
Threshold Voltage ◽  
Flat Band ◽  
Compact Modeling ◽  
Flat Band Voltage ◽  
Physically Based

scholarly journals An Approach For Drain Current Modeling Including Quantum Mechanical Effects For A DMDG Junctionless Field Effect Nanowire Transistor

2021 ◽  
Author(s):  
Nipanka Bora
Keyword(s):  
Surface Potential ◽  
Threshold Voltage ◽  
Field Effect ◽  
Drain Current ◽  
Compact Modeling ◽  
Threshold Voltage Shift ◽  
Nanowire Transistor ◽  
Dual Material ◽  
Potential Threshold ◽  
Drain Conductance

Abstract This paper presents the effects of quantum confinements on the surface potential, threshold voltage, drain current, transconductance, and drain conductance of a Dual Material Double Gate Junctionless Field Effect Nanowire Transistor (DMDG-JLFENT). The carrier energy quantization on the threshold voltage of a DMDG-JLFENT is modeled, and subsequently, other parameters like drain current were analytically presented. The QME considered here is obtained under the quantum confinement condition for an ultra-thin channel, i.e., below 10 nm of Si thickness. The threshold voltage shift due to QME can be used as a quantum correction term for compact modeling of junctionless transistors. The analytical model proposed for surface potential, threshold voltage, drain current, transconductance, and drain conductance were verified by TCAD 3-D quantum simulation results which makes it suitable for SPICE compact modeling.

Sign in / Sign up

Export Citation Format

Share Document