P-Type Floating Gate for Retention and P/E Window Improvement of Flash Memory Devices

2007 ◽  
Vol 54 (8) ◽  
pp. 1910-1917 ◽  
Author(s):  
Chen Shen ◽  
Jing Pu ◽  
Ming-Fu Li ◽  
Byung Jin Cho
Keyword(s):  
Flash Memory ◽  
Floating Gate ◽  
Memory Devices ◽  
P Type

High program efficiency of p-type floating gate in n-channel split-gate embedded flash memory

2008 ◽  
Vol 93 (21) ◽  
pp. 213503 ◽  
Author(s):  
Hung-Sheng Shih ◽  
Shang-Wei Fang ◽  
An-Chi Kang ◽  
Ya-Chin King ◽  
Chrong-Jung Lin
Keyword(s):  
Flash Memory ◽  
Floating Gate ◽  
Program Efficiency ◽  
P Type ◽  
Embedded Flash

CARBON NANOTUBE BASED NONVOLATILE MEMORY DEVICES

2006 ◽  
Vol 16 (04) ◽  
pp. 959-975 ◽  
Author(s):  
YUEGANG ZHANG
Keyword(s):  
Carbon Nanotube ◽  
Flash Memory ◽  
Nonvolatile Memory ◽  
Memory Performance ◽  
Memory Device ◽  
Floating Gate ◽  
Memory Devices ◽  
Memory Cells ◽  
Nonvolatile Memory Devices ◽  
Electrostatic Coupling

The technology progress and increasing high density demand have driven the nonvolatile memory devices into nanometer scale region. There is an urgent need of new materials to address the high programming voltage and current leakage problems in the current flash memory devices. As one of the most important nanomaterials with excellent mechanical and electronic properties, carbon nanotube has been explored for various nonvolatile memory applications. While earlier proposals of "bucky shuttle" memories and nanoelectromechanical memories remain as concepts due to fabrication difficulty, recent studies have experimentally demonstrated various prototypes of nonvolatile memory cells based on nanotube field-effect-transistor and discrete charge storage bits, which include nano-floating gate memory cells using metal nanocrystals, oxide-nitride-oxide memory stack, and more simpler trap-in-oxide memory devices. Despite of the very limited research results, distinct advantages of high charging efficiency at low operation voltage has been demonstrated. Single-electron charging effect has been observed in the nanotube memory device with quantum dot floating gates. The good memory performance even with primitive memory cells is attributed to the excellent electrostatic coupling of the unique one-dimensional nanotube channel with the floating gate and the control gate, which gives extraordinary charge sensibility and high current injection efficiency. Further improvement is expected on the retention time at room temperature and programming speed if the most advanced fabrication technology were used to make the nanotube based memory cells.

Effects of abnormal cell-to-cell interference on p-type floating gate and control gate NAND flash memory

2014 ◽  
Vol 53 (4S) ◽  
pp. 04ED12 ◽  
Author(s):  
Yong Jun Kim ◽  
Jun Geun Kang ◽  
Byungin Lee ◽  
Gyu-Seog Cho ◽  
Sung-Kye Park ◽  
...  
Keyword(s):  
Flash Memory ◽  
Floating Gate ◽  
Nand Flash ◽  
Nand Flash Memory ◽  
Abnormal Cell ◽  
P Type ◽  
And Control

Vertical Flash memory devices with Protein-assembled Nanocrystal floating gate and A12O3 control oxide

2008 ◽  
Author(s):  
F. Ferdousi ◽  
J. Sarkar ◽  
S. Tang ◽  
D. Shahrjerdi ◽  
T. Akyol ◽  
...  
Keyword(s):  
Flash Memory ◽  
Floating Gate ◽  
Memory Devices

Integration Processes and Properties of One Transistor Memory Devices

2002 ◽  
Vol 747 ◽  
Author(s):  
Tingkai Li ◽  
Sheng Teng Hsu ◽  
Bruce Ulrich ◽  
Fengyan Zhang ◽  
Dave Evans
Keyword(s):  
Memory Device ◽  
Floating Gate ◽  
Memory Devices ◽  
Ferroelectric Capacitor ◽  
Gate Electrodes ◽  
Damascene Process ◽  
Polysilicon Gate ◽  
High Etch Rate ◽  
The One ◽  
P Type

ABSTRACTMFMPOS (Metal, Ferroelectrics, Metal, Polysilicon, Oxide, and Silicon) one-transistor (1T) ferroelectric memory devices have been fabricated. However, the yield of 1T-memory devices is lower. We find that the main problems of 1T MFMPOS memory devices are shorts, opens, no memory window, smaller memory windows and blank. In order to solve these problems, we studied the reasons resulted in the problems. Then, the integration processes for one transistor memory device were optimized. Fabrication of nMOSFET 1T memory devices starts with shallow trench isolation (STI) on p-type Si. A gate oxide is thermally grown after p-well implantation. Phosphorus ions were implanted after polysilicon gate definition for the formation of self-aligned source, drain, and n-type floating gate. A damascene process using MOCVD PGO deposition and chemical mechanical polishing (CMP) were used to avoid etching damage. Electrodes for the ferroelectric capacitor, i.e., the floating Ir bottom electrode and Pt top electrode, are deposited by E-Beam evaporation. The area ratio of the top and floating gate electrodes is 1:1. After inter-level dielectric (ILD) deposition, contact etching stops on Pt at gate and on Si at source/drain (S/D) without difficulty because of high etch rate selectively to the Pt. Finally, the high quality 1T memory devices have been made. The one-transistor memory devices showed memory windows around 2 – 3V. The memory windows are almost saturated from operation voltage of 3V. The ratios of “on” state current to the “off” state current are closed to 8 – 9 orders. The one-transistor memory devices also show a very good memory characteristics and retention properties.

Multi-layer high-κ interpoly dielectric for floating gate flash memory devices

2008 ◽  
Vol 52 (4) ◽  
pp. 564-570 ◽  
Author(s):  
Lu Zhang ◽  
Wei He ◽  
Daniel S.H. Chan ◽  
Byung Jin Cho
Keyword(s):  
Flash Memory ◽  
Floating Gate ◽  
Memory Devices
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