A Memory Efficient Partially Parallel Decoder Architecture for Quasi-Cyclic LDPC Codes

Zhongfeng Wang; Zhiqiang Cui

doi:10.1109/ted.2007.895247

A Memory Efficient Partially Parallel Decoder Architecture for Quasi-Cyclic LDPC Codes

IEEE Transactions on Very Large Scale Integration (VLSI) Systems ◽

10.1109/ted.2007.895247 ◽

2007 ◽

Vol 15 (4) ◽

pp. 483-488 ◽

Cited By ~ 30

Author(s):

Zhongfeng Wang ◽

Zhiqiang Cui

Keyword(s):

Ldpc Codes ◽

Decoder Architecture ◽

Memory Efficient

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A Memory Efficient Partially Parallel Decoder Architecture for QC-LDPC Codes

Conference Record of the Thirty-Ninth Asilomar Conference onSignals, Systems and Computers, 2005. ◽

10.1109/acssc.2005.1599848 ◽

2006 ◽

Cited By ~ 4

Author(s):

Zhongfeng Wang ◽

Zhiqiang Cui

Keyword(s):

Ldpc Codes ◽

Decoder Architecture ◽

Memory Efficient

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A Fast-Convergence Decoding Method and Memory-Efficient VLSI Decoder Architecture for Irregular LDPC Codes in the IEEE 802.16e Standards

2007 IEEE 66th Vehicular Technology Conference ◽

10.1109/vetecf.2007.269 ◽

2007 ◽

Cited By ~ 2

Author(s):

Yeong-Luh Ueng ◽

Chung-Chao Cheng

Keyword(s):

Ldpc Codes ◽

Fast Convergence ◽

Ieee 802.16E ◽

Decoder Architecture ◽

Irregular Ldpc Codes ◽

Memory Efficient

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Parallel turbo-sum-product decoder architecture for quasi-cyclic LDPC codes

Proceedings of the 16th ACM Great Lakes symposium on VLSI - GLSVLSI '06 ◽

10.1145/1127908.1127980 ◽

2006 ◽

Cited By ~ 3

Author(s):

Yongmei Dai ◽

Zhiyuan Yan ◽

Ning Chen

Keyword(s):

Ldpc Codes ◽

Decoder Architecture

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A Memory-Efficient Block-wise MAP Decoder Architecture

ETRI Journal ◽

10.4218/etrij.04.0103.0091 ◽

2004 ◽

Vol 26 (6) ◽

pp. 615-621 ◽

Cited By ~ 1

Author(s):

Sik Kim ◽

Sun-Young Hwang ◽

Moon Jun Kang

Keyword(s):

Decoder Architecture ◽

Map Decoder ◽

Memory Efficient

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Memory-Efficient Sum–Product Decoding of LDPC Codes

IEEE Transactions on Communications ◽

10.1109/tcomm.2004.833016 ◽

2004 ◽

Vol 52 (8) ◽

pp. 1225-1230 ◽

Cited By ~ 17

Author(s):

H. Sankar ◽

K.R. Narayanan

Keyword(s):

Ldpc Codes ◽

Memory Efficient

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Efficient Shuffled Decoder Architecture for Nonbinary Quasi-Cyclic LDPC Codes

IEEE Transactions on Very Large Scale Integration (VLSI) Systems ◽

10.1109/tvlsi.2012.2218839 ◽

2013 ◽

Vol 21 (9) ◽

pp. 1756-1761 ◽

Cited By ~ 15

Author(s):

Jun Lin ◽

Zhiyuan Yan

Keyword(s):

Ldpc Codes ◽

Decoder Architecture

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Half-row modified two-extra-column trellis min-max decoder architecture for nonbinary LDPC codes

Integration ◽

10.1016/j.vlsi.2019.04.005 ◽

2019 ◽

Vol 69 ◽

pp. 234-241

Author(s):

Huyen Pham Thi ◽

Hanho Lee ◽

Xuan Nghia Pham

Keyword(s):

Ldpc Codes ◽

Decoder Architecture ◽

Nonbinary Ldpc Codes

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An LDPC decoder architecture for multi-rate QC-LDPC codes

2011 IEEE 54th International Midwest Symposium on Circuits and Systems (MWSCAS) ◽

10.1109/mwscas.2011.6026376 ◽

2011 ◽

Cited By ~ 3

Author(s):

Sung-Woo Choi ◽

Gyung-Pyo Kim ◽

Jin-Kyeong Kim

Keyword(s):

Ldpc Codes ◽

Ldpc Decoder ◽

Decoder Architecture

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Memory-efficient turbo decoder architectures for LDPC codes

IEEE Workshop on Signal Processing Systems ◽

10.1109/sips.2002.1049702 ◽

2003 ◽

Cited By ~ 21

Author(s):

M.M. Mansour ◽

N.R. Shanbhag

Keyword(s):

Ldpc Codes ◽

Turbo Decoder ◽

Memory Efficient

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A High Speed, Low Memory FPGA Based LDPC Decoder Architecture for Quasi-Cyclic LDPC Codes

2006 International Conference on Field Programmable Logic and Applications ◽

10.1109/fpl.2006.311328 ◽

2006 ◽

Cited By ~ 2

Author(s):

Paul Saunders ◽

Anthony Fagan

Keyword(s):

High Speed ◽

Ldpc Codes ◽

Ldpc Decoder ◽

Decoder Architecture

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