A Fast-Convergence Decoding Method and Memory-Efficient VLSI Decoder Architecture for Irregular LDPC Codes in the IEEE 802.16e Standards

2007 IEEE 66th Vehicular Technology Conference ◽

10.1109/vetecf.2007.269 ◽

2007 ◽

Cited By ~ 2

Author(s):

Yeong-Luh Ueng ◽

Chung-Chao Cheng

Keyword(s):

Ldpc Codes ◽

Fast Convergence ◽

Ieee 802.16E ◽

Decoder Architecture ◽

Irregular Ldpc Codes ◽

Memory Efficient

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A Memory Efficient Partially Parallel Decoder Architecture for QC-LDPC Codes

Conference Record of the Thirty-Ninth Asilomar Conference onSignals, Systems and Computers, 2005. ◽

10.1109/acssc.2005.1599848 ◽

2006 ◽

Cited By ~ 4

Author(s):

Zhongfeng Wang ◽

Zhiqiang Cui

Keyword(s):

Ldpc Codes ◽

Decoder Architecture ◽

Memory Efficient

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A Memory Efficient Partially Parallel Decoder Architecture for Quasi-Cyclic LDPC Codes

IEEE Transactions on Very Large Scale Integration (VLSI) Systems ◽

10.1109/ted.2007.895247 ◽

2007 ◽

Vol 15 (4) ◽

pp. 483-488 ◽

Cited By ~ 30

Author(s):

Zhongfeng Wang ◽

Zhiqiang Cui

Keyword(s):

Ldpc Codes ◽

Decoder Architecture ◽

Memory Efficient

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Design and Construction of Irregular LDPC Codes for Channels with Synchronization Errors: New Aspect of Degree Profiles

IEICE Transactions on Fundamentals of Electronics Communications and Computer Sciences ◽

10.1587/transfun.2020eap1004 ◽

2020 ◽

Vol E103.A (10) ◽

pp. 1237-1247

Author(s):

Ryo SHIBATA ◽

Gou HOSOYA ◽

Hiroyuki YASHIMA

Keyword(s):

Ldpc Codes ◽

Synchronization Errors ◽

Irregular Ldpc Codes ◽

Design And Construction

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Parallel turbo-sum-product decoder architecture for quasi-cyclic LDPC codes

Proceedings of the 16th ACM Great Lakes symposium on VLSI - GLSVLSI '06 ◽

10.1145/1127908.1127980 ◽

2006 ◽

Cited By ~ 3

Author(s):

Yongmei Dai ◽

Zhiyuan Yan ◽

Ning Chen

Keyword(s):

Ldpc Codes ◽

Decoder Architecture

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Optimal rate for irregular LDPC codes in binary erasure channel

2011 IEEE Information Theory Workshop ◽

10.1109/itw.2011.6089360 ◽

2011 ◽

Cited By ~ 5

Author(s):

H. Tavakoli ◽

M. Ahmadian Attari ◽

M. Reza Peyghami

Keyword(s):

Ldpc Codes ◽

Optimal Rate ◽

Irregular Ldpc Codes ◽

Erasure Channel ◽

Binary Erasure Channel

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Design of irregular LDPC codes for BIAWGN channels with SNR mismatch

IEEE Transactions on Communications ◽

10.1109/tcomm.2009.0901.060118 ◽

2009 ◽

Vol 57 (1) ◽

pp. 6-11 ◽

Cited By ~ 12

Author(s):

Hamid Saeedi ◽

Amir H. Banihashemi

Keyword(s):

Ldpc Codes ◽

Irregular Ldpc Codes

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FPGA Implementation of Decoder Architectures for High Throughput Irregular LDPC Codes

Indian Journal of Science and Technology ◽

10.17485/ijst/2016/v9i48/97269 ◽

2016 ◽

Vol 9 (48) ◽

Cited By ~ 1

Author(s):

Sandeep Kakde ◽

Atish Khobragade ◽

M. D. Ekbal Husain

Keyword(s):

High Throughput ◽

Ldpc Codes ◽

Fpga Implementation ◽

Irregular Ldpc Codes

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Design of structured irregular LDPC codes

2008 IEEE Region 8 International Conference on Computational Technologies in Electrical and Electronics Engineering ◽

10.1109/sibircon.2008.4602580 ◽

2008 ◽

Cited By ~ 2

Author(s):

Peter Trifonov

Keyword(s):

Ldpc Codes ◽

Irregular Ldpc Codes

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A thresholding algorithm for improved split-row decoding method of irregular LDPC codes

2015 Intelligent Systems and Computer Vision (ISCV) ◽

10.1109/isacv.2015.7106166 ◽

2015 ◽

Cited By ~ 2

Author(s):

Rachid El Alami ◽

Hassan Qjidaa ◽

Youness Mehdaoui ◽

Mostafa Mrabti

Keyword(s):

Ldpc Codes ◽

Irregular Ldpc Codes ◽

Thresholding Algorithm

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Lowering Error Floors of Irregular LDPC Codes by Combining Construction and Decoding

IEICE Transactions on Communications ◽

10.1587/transcom.e95.b.271 ◽

2012 ◽

Vol E95-B (1) ◽

pp. 271-274 ◽

Cited By ~ 1

Author(s):

Xiaopeng JIAO ◽

Jianjun MU ◽

Fan FANG ◽

Rong SUN

Keyword(s):

Ldpc Codes ◽

Irregular Ldpc Codes ◽

Error Floors

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