Memory-efficient turbo decoder architectures for LDPC codes

IEEE Workshop on Signal Processing Systems ◽

10.1109/sips.2002.1049702 ◽

2003 ◽

Cited By ~ 21

Author(s):

M.M. Mansour ◽

N.R. Shanbhag

Keyword(s):

Ldpc Codes ◽

Turbo Decoder ◽

Memory Efficient

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Memory-Efficient Sum–Product Decoding of LDPC Codes

IEEE Transactions on Communications ◽

10.1109/tcomm.2004.833016 ◽

2004 ◽

Vol 52 (8) ◽

pp. 1225-1230 ◽

Cited By ~ 17

Author(s):

H. Sankar ◽

K.R. Narayanan

Keyword(s):

Ldpc Codes ◽

Memory Efficient

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Memory efficient column-layered decoder design for non-binary LDPC codes

2012 IEEE International Symposium on Circuits and Systems ◽

10.1109/iscas.2012.6271841 ◽

2012 ◽

Author(s):

Kai He ◽

Jin Sha ◽

Zhongfeng Wang

Keyword(s):

Ldpc Codes ◽

Efficient Column ◽

Decoder Design ◽

Memory Efficient

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Memory Efficient Decoder Architectures for Quasi-Cyclic LDPC Codes

IEEE Transactions on Circuits and Systems I Regular Papers ◽

10.1109/tcsi.2008.922024 ◽

2008 ◽

Vol 55 (9) ◽

pp. 2898-2911 ◽

Cited By ~ 28

Author(s):

Yongmei Dai ◽

Ning Chen ◽

Zhiyuan Yan

Keyword(s):

Ldpc Codes ◽

Memory Efficient

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A Parallel and Memory-Efficient Decoding for Spatially-Coupled LDPC Codes

2020 IEEE/CIC International Conference on Communications in China (ICCC) ◽

10.1109/iccc49849.2020.9238855 ◽

2020 ◽

Author(s):

Qihao Wu ◽

Lihong Lv ◽

Yanjun Yao ◽

Sheng Wu

Keyword(s):

Ldpc Codes ◽

Memory Efficient ◽

Efficient Decoding

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A memory efficient scheme for hardware implementation of log-MAP turbo decoder

IEEE VTS 53rd Vehicular Technology Conference, Spring 2001. Proceedings (Cat. No.01CH37202) ◽

10.1109/vetecs.2001.944595 ◽

2002 ◽

Author(s):

Chunlong Bai ◽

Jun Jiang ◽

Ping Zhang

Keyword(s):

Hardware Implementation ◽

Turbo Decoder ◽

Efficient Scheme ◽

Log Map ◽

Memory Efficient

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Memory-efficient decoding of LDPC codes

Proceedings. International Symposium on Information Theory, 2005. ISIT 2005. ◽

10.1109/isit.2005.1523376 ◽

2005 ◽

Cited By ~ 29

Author(s):

J.K.-S. Lee ◽

J. Thorpe

Keyword(s):

Ldpc Codes ◽

Memory Efficient ◽

Efficient Decoding

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Memory efficient layered decoder design with early termination for LDPC codes

2011 IEEE International Symposium of Circuits and Systems (ISCAS) ◽

10.1109/iscas.2011.5938161 ◽

2011 ◽

Cited By ~ 7

Author(s):

Jiangpeng Li ◽

Guanghui He ◽

Hexi Hou ◽

Zhejun Zhang ◽

Jun Ma

Keyword(s):

Ldpc Codes ◽

Early Termination ◽

Decoder Design ◽

Memory Efficient

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A Memory Efficient Partially Parallel Decoder Architecture for QC-LDPC Codes

Conference Record of the Thirty-Ninth Asilomar Conference onSignals, Systems and Computers, 2005. ◽

10.1109/acssc.2005.1599848 ◽

2006 ◽

Cited By ~ 4

Author(s):

Zhongfeng Wang ◽

Zhiqiang Cui

Keyword(s):

Ldpc Codes ◽

Decoder Architecture ◽

Memory Efficient

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A Memory Efficient Partially Parallel Decoder Architecture for Quasi-Cyclic LDPC Codes

IEEE Transactions on Very Large Scale Integration (VLSI) Systems ◽

10.1109/ted.2007.895247 ◽

2007 ◽

Vol 15 (4) ◽

pp. 483-488 ◽

Cited By ~ 30

Author(s):

Zhongfeng Wang ◽

Zhiqiang Cui

Keyword(s):

Ldpc Codes ◽

Decoder Architecture ◽

Memory Efficient

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Memory efficient EMS decoding for non-binary LDPC codes

2013 IEEE International Symposium on Circuits and Systems (ISCAS2013) ◽

10.1109/iscas.2013.6572101 ◽

2013 ◽

Author(s):

Leixin Zhou ◽

Jin Sha ◽

Yun Chen ◽

Zhongfeng Wang

Keyword(s):

Ldpc Codes ◽

Memory Efficient

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