A High Speed, Low Memory FPGA Based LDPC Decoder Architecture for Quasi-Cyclic LDPC Codes

2006 ◽  
Author(s):  
Paul Saunders ◽  
Anthony Fagan
Keyword(s):  
High Speed ◽  
Ldpc Codes ◽  
Ldpc Decoder ◽  
Decoder Architecture

scholarly journals LDPC Decoder of High Speed Multi-Rate DVB-S2 Based on FPGA

2019 ◽  
Vol 37 (2) ◽  
pp. 299-307 ◽  
Author(s):  
TianJiao Xie ◽  
Bo Li ◽  
Mao Yang ◽  
Zhongjiang Yan
Keyword(s):  
High Speed ◽  
State Of The Art ◽  
Ldpc Codes ◽  
The State ◽  
Elementary Transformation ◽  
Parity Check ◽  
Ldpc Decoder ◽  
Art Works ◽  
Decoder Architecture ◽  
Lower Triangular

A multi-rate LDPC decoder architecture for DVB-S2 codes based on FPGA is proposed. Through elementary transformation on the parity check matrices of DVB-S2 LDPC codes, a new matrix whose left is a QC sub-matrix and right is Transformation of Staircase lower triangular (TST) sub-matrix is obtained. The QC and TST are designed separately, therefore the successful experience of the most popular Quasi-Cyclic (QC) LDPC decoder architecture can be drawn on. While for TST sub-matrix, the variable nodes updating only need to be considered and the check nodes updating is realized compatibility with QC sub-matrix. Based on the proposed architectures, a multi-rate LDPC decoder implemented on Xilinx XC7VX485T FPGA can achieve the maximum decoding throughput of 2.5 Gbit/s at the 20 iterations when the operating frequency is 250 MHz, which demonstrates the highest throughput compared with the state-of-the-art works.

scholarly journals Memory Compact High-Speed QC-LDPC Decoder Based on FPGA

2019 ◽  
Vol 37 (3) ◽  
pp. 515-522
Author(s):  
Tianjiao Xie ◽  
Bo Li ◽  
Mao Yang ◽  
Zhongjiang Yan
Keyword(s):  
High Speed ◽  
Clock Cycle ◽  
Fpga Implementation ◽  
Maximum Frequency ◽  
Ldpc Decoder ◽  
Memory Strategies ◽  
Multiple Data ◽  
Decoder Architecture ◽  
Place And Route ◽  
Area Efficient

In this paper, two compact memory strategies for partially parallel QC-LDPC decoder architecture are proposed. By compacting several adjacent rows hard decisions and extrinsic messages into one memory entry, which not only reduces the number of memory banks for hard decisions, but also facilitates multiple data accesses per clock cycle so as to increase the throughput of decoder. We demonstrate significant high speed and area efficient benefits of using the proposed techniques with an FPGA implementation of a CCSDS LDPC decoder on Xilinx XC5VLX330 device. The result shows that our new decoder can operate at a maximum frequency of 250 MHz after place and route, and achieve a throughput up to 2 Gb/s at 14 iterations.

An Efficient VLSI Architecture for Nonbinary LDPC Decoder with Adaptive Message Control

2015 ◽  
Vol 4 (1) ◽  
pp. 6
Author(s):  
Varatharajan Ramachandran
Keyword(s):  
Power Consumption ◽  
Vlsi Architecture ◽  
Ldpc Codes ◽  
Parity Check ◽  
Decoding Complexity ◽  
Ldpc Decoder ◽  
Message Length ◽  
Low Density Parity Check ◽  
Decoder Architecture ◽  
Memory Accesses

<p>A new decoder architecture for nonbinary low-density parity check (LDPC) codes is presented in this paper to reduce the hardware operational complexity and power consumption. Adaptive message control (AMC) is to achieve the low decoding complexity,  that dynamically trims the message length of belief information to reduce the amount of memory accesses and arithmetic operations. A new horizontal nonbinary LDPC decoder architecture is developed to implement AMC. Key components in the architecture have been designed with the consideration of variable message lengths to leverage the benefit of the proposed AMC. Simulation results demonstrate that the proposed nonbinary LDPC decoder architecture can significantly reduce hardware operations and power consumption as compared with existing work with negligible performance degradation.</p>

Implementation of Decoder for Effective Quasi-Cyclic LDPC Codes Based on FPGA

2013 ◽  
Vol 791-793 ◽  
pp. 1867-1871
Author(s):  
Ji Qu Han ◽  
Li Liu
Keyword(s):  
High Speed ◽  
Ldpc Codes ◽  
Parity Check ◽  
Decoding Algorithm ◽  
Parity Check Matrix ◽  
Throughput Rate ◽  
Triangular Structure ◽  
Check Matrix ◽  
Decoder Architecture ◽  
Lower Triangular

Designers are increasingly relying on FPGA-based emulation to evaluate the performance of LDPC codes. In this paper, we propose a novel approximate lower triangular structure for the parity part of the parity-check matrix of QC-LDPC codes. Next, a high speed partially parallel decoder architecture which based on the Offset BP-based decoding algorithm is proposed. The results indicate that the frequency can reach 100MHz and its throughput rate can reach 113Mbps.

IMPLEMENTATION OF SOME DECODING ALGORITHMS FOR NB-LDPC CODES ON FPGA

2020 ◽  
pp. 1-10
Author(s):  
Thuan
Keyword(s):  
Error Correction ◽  
Communication Systems ◽  
High Speed ◽  
Ldpc Codes ◽  
Ldpc Decoder ◽  
Decoding Algorithms ◽  
Analysis And Evaluation ◽  
Check Node ◽  
Parity Check Codes ◽  
Very High

Non-binary low-density parity-check codes (NB-LDPC) provide better error correction performance in comparison with their counterparts. However, the NB-LDPC decoder has a very high complexity, especially the processing of the check node unit. This paper evaluates the error correction performance of some decoding algorithms for NB-LDPC codes in different fields with different codeword lengths. The paper also presents the results of the implementation a decoder structure for the NB-LDPC (35,23) over GF(8) on the Spartan 6 board. Analysis and evaluation results show that decoding quality on hardware is equivalent to simulation results on software, demonstrating high feasibility in implementing decoder on a hardware platform, capable of application in devices of the advanced communication systems or high-speed read-and-write data storages.

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