Testing and Diagnostics of CMOS Circuits Using Light Emission from Off-State Leakage Current

2004 ◽  
Vol 51 (9) ◽  
pp. 1455-1462 ◽  
Author(s):  
F. Stellari ◽  
P. Song ◽  
J.C. Tsang ◽  
M.K. McManus ◽  
M.B. Ketchen
Keyword(s):  
Leakage Current ◽  
Light Emission ◽  
Cmos Circuits

Three-Color Passive-Matrix Pixels Using Dye-Diffusion-Patterned Tri-Layer Polymer-Based LED

2001 ◽  
Vol 708 ◽  
Author(s):  
Ke Long ◽  
Florian Pschenitzka ◽  
J. C. Sturm
Keyword(s):  
Leakage Current ◽  
Light Emission ◽  
Layer Structure ◽  
Single Layer ◽  
Transport Layer ◽  
Electron Transport Layer ◽  
Reverse Leakage Current ◽  
Dye Diffusion ◽  
Current Rectification ◽  
Doped Polymer

ABSTRACTDry dye-printing and solvent-enhanced dye diffusion were used to locally dope a previously spin-coated poly(9-vinylcarbazole) (PVK) polymer film with different dyes to fabricate side-by-side RGB OLED pixels. To reduce reverse leakage current and raise efficiency, a blanket tris-8-hydroxyquinoline aluminum (Alq) electron transport layer (ETL) was deposited over the polymer layer after the dye diffusion step, along with a 2,9-dimethyl-4,7-diphenyl-1,10-phenanthroline (BCP) hole/exciton blocking layer between the Alq and the PVK to ensure all light emission occurred from the doped polymer and not from the Alq. Devices with this tri-layer structure have an extremely low reverse leakage current (rectification ratio of 106 at +/- 10V) and a higher external quantum efficiency (∼1%) than single layer devices. A three-color passive-matrix test array with 300μm x 1mm RGB subpixels was demonstrated with this structure.

scholarly journals Leakage Current Reduction in CMOS Circuits Using Stacking Technique

2020 ◽  
pp. 175-178
Author(s):  
N. Geetha Rani ◽  
G. Ragapriya ◽  
Harshitha V ◽  
G. Swetha ◽  
B. Sri Jyothi
Keyword(s):  
Leakage Current ◽  
Leakage Power ◽  
Cmos Circuits ◽  
Rapid Progress ◽  
Semiconductor Technology ◽  
Single Chip ◽  
Leakage Currents ◽  
Current Reduction

This paper deals with The rapid progress in semiconductor technology have led the feature sizes of transistor to be shrunk there by evolution of Deep Sub-Micron (DSM) technology. There by the extremely complex functionality is enabled to be integrated on a single chip. So, transistor size is reduced to few nanometers. By reducing the size drastically some problems are occurred. In that leakage power is one of the disadvantage. By using this stacking technique we are going to reduce the leakage currents.

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