scholarly journals Leakage Current Reduction in CMOS Circuits Using Stacking Technique

2020 ◽  
pp. 175-178
Author(s):  
N. Geetha Rani ◽  
G. Ragapriya ◽  
Harshitha V ◽  
G. Swetha ◽  
B. Sri Jyothi
Keyword(s):  
Leakage Current ◽  
Leakage Power ◽  
Cmos Circuits ◽  
Rapid Progress ◽  
Semiconductor Technology ◽  
Single Chip ◽  
Leakage Currents ◽  
Current Reduction

This paper deals with The rapid progress in semiconductor technology have led the feature sizes of transistor to be shrunk there by evolution of Deep Sub-Micron (DSM) technology. There by the extremely complex functionality is enabled to be integrated on a single chip. So, transistor size is reduced to few nanometers. By reducing the size drastically some problems are occurred. In that leakage power is one of the disadvantage. By using this stacking technique we are going to reduce the leakage currents.

scholarly journals Forced stack sleep transistor (FORTRAN): A new leakage current reduction approach in CMOS based circuit designing

2021 ◽  
Vol 34 (2) ◽  
pp. 259-280
Author(s):  
Sankit Kassa ◽  
Neeraj Misra ◽  
Rajendra Nagaria
Keyword(s):  
Low Power ◽  
Leakage Current ◽  
Power Efficiency ◽  
High Performance ◽  
Low Voltage ◽  
Full Adder ◽  
Leakage Power ◽  
Modes Of Operation ◽  
Power Circuit ◽  
Current Reduction

Reduction in leakage current has become a significant concern in nanotechnology-based low-power, low-voltage, and high-performance VLSI applications. This research article discusses a new low-power circuit design the approach of FORTRAN (FORced stack sleep TRANsistor), which decreases the leakage power efficiency in the CMOS-based circuit outline in VLSI domain. FORTRAN approach reduces leakage current in both active as well as standby modes of operation. Furthermore, it is not time intensive when the circuit goes from active mode to standby mode and vice-versa. To validate the proposed design approach, experiments are conducted in the Tanner EDA tool of mentor graphics bundle on projected circuit designs for the full adder, a chain of 4-inverters, and 4- bit multiplier designs utilizing 180nm, 130nm, and 90nm TSMC technology node. The outcomes obtained show the result of a 95-98% vital reduction in leakage power as well as a 15-20% reduction in dynamic power with a minor increase in delay. The result outcomes are compared for accuracy with the notable design approaches that are accessible for both active and standby modes of operation.

Leakage Current Reduction of Ni-MILC Poly-Si TFT Using Chemical Cleaning Method

2018 ◽  
Vol 28 (8) ◽  
pp. 440-444
Author(s):  
Kwang-Jin Lee ◽  
◽  
Doyeon Kim ◽  
Duck-Kyun Choi ◽  
Woo-Byoung Kim
Keyword(s):  
Leakage Current ◽  
Chemical Cleaning ◽  
Cleaning Method ◽  
Current Reduction

Organic synaptic devices based on ionic gel with reduced leakage current

2021 ◽  
Vol 57 (15) ◽  
pp. 1907-1910
Author(s):  
Dapeng Liu ◽  
Yiwei Zhao ◽  
Qianqian Shi ◽  
Shilei Dai ◽  
Li Tian ◽  
...  
Keyword(s):  
Solid State ◽  
Leakage Current ◽  
Dielectric Film ◽  
Neuromorphic Computing ◽  
Computing Systems ◽  
Current Reduction

A solid-state hybrid electrolyte dielectric film was designed for leakage current reduction, synaptic simulation and neuromorphic computing systems.

A Single-Phase Five-Level Transformer-Less PV Inverter for Leakage Current Reduction

2021 ◽  
pp. 1-1
Author(s):  
Xiaonan Zhu ◽  
Hongliang Wang ◽  
Wenyuan Zhang ◽  
Hanzhe Wang ◽  
Xiaojun Deng ◽  
...  
Keyword(s):  
Leakage Current ◽  
Single Phase ◽  
Pv Inverter ◽  
Current Reduction

APPLICATION OF EPITAXIAL UNIPOLAR BARRIERS TO REDUCE NOISE CURRENTS IN PHOTODETECTORS

2011 ◽  
Vol 20 (03) ◽  
pp. 557-564
Author(s):  
G. R. SAVICH ◽  
J. R. PEDRAZZANI ◽  
S. MAIMON ◽  
G. W. WICKS
Keyword(s):  
Leakage Current ◽  
Surface Passivation ◽  
Leakage Currents ◽  
Type Region ◽  
Surface Leakage Current ◽  
Unipolar Barrier ◽  
Trap Assisted Tunneling ◽  
Assisted Tunneling ◽  
Tunneling Currents ◽  
Surface Leakage

Tunneling currents and surface leakage currents are both contributors to the overall dark current which limits many semiconductor devices. Surface leakage current is generally controlled by applying a post-epitaxial passivation layer; however, surface passivation is often expensive and ineffective. Band-to-band and trap assisted tunneling currents cannot be controlled through surface passivants, thus an alternative means of control is necessary. Unipolar barriers, when appropriately applied to standard electronic device structures, can reduce the effects of both surface leakage and tunneling currents more easily and cost effectively than other methods, including surface passivation. Unipolar barriers are applied to the p -type region of a conventional, MBE grown, InAs based pn junction structures resulting in a reduction of surface leakage current. Placing the unipolar barrier in the n -type region of the device, has the added benefit of reducing trap assisted tunneling current as well as surface leakage currents. Conventional, InAs pn junctions are shown to exhibit surface leakage current while unipolar barrier photodiodes show no detectable surface currents.

Protection of railway infrastructure objects against electrical corrosion

2021 ◽  
Vol ahead-of-print (ahead-of-print) ◽  
Author(s):  
Liudmyla Trykoz ◽  
Svetlana Kamchatnaya ◽  
Dmytro Borodin ◽  
Armen Atynian ◽  
Roman Tkachenko
Keyword(s):  
Leakage Current ◽  
Electrical Resistance ◽  
Electrical Current ◽  
Leakage Currents ◽  
Destructive Effect ◽  
Accelerated Corrosion ◽  
Content Type ◽  
Pedestrian Bridges ◽  
Railway Infrastructure ◽  
Bridge Structures

Purpose The purpose of this paper is to develop a technological method of protection against electrical corrosion. One more way to protect the objects is to prevent the electrical current from getting to them. For example, railway objects are surrounded with a material with raised electrical resistance. Design/methodology/approach The railway infrastructure objects (foundations, contact-line supports, reinforced concrete sub-bases, bridge structures, pipelines of engineering networks, supports of passenger platforms and pedestrian bridges, concrete plinth walls of station buildings) are subjected to destruction due to the action of electrical current. One of destruction factors is a corrosion of the concrete constructions which is caused by the leakage current action. Findings Leakage currents and stray currents bypass the structure of supports of high passenger platforms or pipes of engineering networks. These currents spread by the line with the least resistance outside of the structures. Research limitations/implications Electrical leakage current from the rails gets into such structures through sleepers, ballast and soil and leads to accelerated corrosion leaching of concrete. Practical implications The constructions are protected against the destructive effect of electrical corrosion on the metal or concrete of the structure. This scheme is suitable for the construction and reconstruction of railway structures which operate on electrified sections of railways. Originality/value Schemes of technological solution are proposed for protection of foundations, supports of high passenger platforms, pipelines of engineering networks, etc. For this, the arrangement of soil-contained screens with big electrical resistance is suggested.

scholarly journals KLECTOR: Design of Low Power Static Random-Access Memory Architecture with reduced Leakage Current

2021 ◽  
Author(s):  
Ananth Kumar Tamilarasan ◽  
Darwin Sundarapandi Edward ◽  
Arun Samuel Thankamony Sarasam
Keyword(s):  
Leakage Current ◽  
Random Access ◽  
Static Random Access Memory ◽  
Memory Architecture ◽  
Access Memory ◽  
Leakage Currents ◽  
Output Node ◽  
Voltage Drops ◽  
Novel Approach ◽  
Standby Mode

Abstract A novel approach called Keeper in LEakage Control Transistor (KLECTOR) is presented in this paper to reduce leakage currents in SRAM architecture. The SRAM is significantly affected by the leakage current during the "standby mode", which is caused by the fabric which has a lower threshold voltage. KLECTOR circuit employs less power consumption by restricting the flow of current through devices of less voltage drops and relies heavily on the self-controlled transistor at the output node. It has been found from the presented results that static (leakage) power in the write operation is reduced to 63% and 69 % for the read operation. This proposed approach is designed and simulated using the Virtuoso, Cadence EDA tool.

scholarly journals Studi Pola Arus Bocor Isolator Keramik Selama Waktu Pemakaian 24 Jam

2020 ◽  
Vol 3 (3) ◽  
Author(s):  
Dini Fauziah ◽  
Waluyo Waluyo ◽  
Ismail Muhammad Khaidir
Keyword(s):  
Ambient Temperature ◽  
Electric Power ◽  
Leakage Current ◽  
Distribution System ◽  
Power Transmission ◽  
Current Data ◽  
Electric Power System ◽  
Leakage Currents ◽  
Ceramic Insulator ◽  
Distribution System Reliability

ABSTRAK Isolator merupakan komponen yang penting dijaga keandalannya dalam sistem transmisi dan distribusi tenaga listrik. Isolator rentan mengalami kegagalan akibat lingkungan, karena terpapar langsung kondisi dimana isolator tersebut terpasang. Salah satu jenis isolator yang sering digunakan adalah bahan keramik, dimana memiliki kelebihan diantaranya kekuatan mekanik yang cukup handal. Namun kekurangan isolator jenis ini adalah sifat permukaannya yang hidrofilik, yaitu mudah menyerap air sehingga bila digunakan pada kelembaban tinggi cenderung memicu timbulnya arus bocor. Arus bocor merupakan parameter penting pada isolator karena sering menjadi penyebab kegagalan isolator. Untuk mengetahui seberapa besar pengaruh kondisi lingkungan terhadap arus bocor, dilakukan pengujian terhadap isolator keramik dalam waktu 24 jam. Data arus bocor diambil setiap 3 jam untuk melihat perubahannya berdasarkan perubahan kelembaban, dan suhu lingkungan. Hasilnya didapat bahwa semakin tinggi kelembaban udara, dan semakin rendah suhu lingkungan maka arus bocor semakin tinggi. Hasil penelitian ini dapat dijadikan acuan untuk mengantisipasi kegagalan isolator keramik akibat arus bocor sehingga keandalan sistem tenaga listrik dapat terjaga. Kata kunci: Isolator keramik, Lingkungan, Kelembaban, Suhu. ABSTRACT Isolator is an important component that must be maintained to keep electric power transmission and distribution system reliability. Isolators are susceptible to failure due to the environment, because they are directly exposed to conditions where the insulator installed. Ceramic insulator is one type of isolator that is often used, which has advantages including mechanical strength that is quite reliable. However, the lack of this type of isolator is its hydrophilic surface, which is easy to absorb water so that when used at high humidity tends to trigger a leakage current. Leakage current is an important parameter in an insulator because it can be a cause due to insulator failure. To find out how environmental conditions impact on leakage currents along day, a ceramic isolator is tested within 24 hours. Leakage current data is taken every 3 hours to see the changes based on changes in humidity, and ambient temperature. The result is the higher humidity of the air, and the lower ambient temperature, can make insulator leakage current rise up. The results of this study can be used as a reference to anticipate the failure of ceramic insulators due to leakage currents so that the reliability of the electric power system can be maintained. Keywords: ceramic insulator, environtment, humidity, temperature.

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