Experimental investigation of tunnel oxide thickness on charge transport through Si nanocrystal dot floating gate memories

2006 ◽  
Vol 24 (3) ◽  
pp. 1271 ◽  
Author(s):  
Prakaipetch Punchaipetch ◽  
Kazunori Ichikawa ◽  
Yukiharu Uraoka ◽  
Takashi Fuyuki ◽  
Atsushi Tomyo ◽  
...  
Keyword(s):  
Experimental Investigation ◽  
Charge Transport ◽  
Oxide Thickness ◽  
Floating Gate ◽  
Si Nanocrystal

Effect of SiO2Tunnel Oxide Thickness on Electron Tunneling Mechanism in Si Nanocrystal Dots Floating-Gate Memories

2006 ◽  
Vol 45 (5A) ◽  
pp. 3997-3999 ◽  
Author(s):  
Prakaipetch Punchaipetch ◽  
Kazunori Ichikawa ◽  
Yukiharu Uraoka ◽  
Takashi Fuyuki ◽  
Eiji Takahashi ◽  
...  
Keyword(s):  
Electron Tunneling ◽  
Oxide Thickness ◽  
Floating Gate ◽  
Tunneling Mechanism ◽  
Si Nanocrystal

Threshold Voltage Shift in Hetero-nanocystal Floating Gate Flash Memory

2004 ◽  
Vol 832 ◽  
Author(s):  
Yan Zhu ◽  
Dengtao Zhao ◽  
Ruigang Li ◽  
Jianlin Liu
Keyword(s):  
Threshold Voltage ◽  
Flash Memory ◽  
Oxide Thickness ◽  
Memory Device ◽  
Floating Gate ◽  
Threshold Voltage Shift ◽  
Voltage Shift ◽  
Poisson Boltzmann ◽  
Poisson Boltzmann Equation ◽  
Dot Density

ABSTRACTThe threshold voltage shift of a p-channel Ge/Si hetero-nanocrystal floating gate memory device was investigated both numerically and phenomenologically. The numerical investigations, by solving 2-D Poisson-Boltzmann equation, show that the presence of the Ge on Si dot tremendously prolongs the retention time, reflected by the time decay behavior of the threshold voltage shift. The increase of the thickness of either Si or Ge dot will reduce the threshold voltage shift. The shift strongly depends on the dot density. Nevertheless, only a weak relation between the threshold voltage shift and the tunneling oxide thickness was found. A circuit model was then introduced to interpret the behavior of threshold voltage shift, which agrees well with the results of the numerical method.

scholarly journals Some Considerations on Tunneling Losses in Field-Effect Devices for Low-Voltage Microcontrollers

1998 ◽  
Vol 21 (1) ◽  
pp. 57-60 ◽  
Author(s):  
M. A. Grado-Caffaro ◽  
M. Grado-Caffaro
Keyword(s):  
Electric Field ◽  
Oxide Layer ◽  
Power Density ◽  
Field Effect ◽  
Low Voltage ◽  
Tunneling Current ◽  
Oxide Thickness ◽  
High Electric Field ◽  
Floating Gate ◽  
Field Effect Devices

The loss power density associated with the tunneling current in a typical MOS cell with a floating gate is evaluated for high electric-field strengths in the oxide layer. Furthermore, problems related to oxide thickness are discussed.

Theoretical and experimental investigation of Si nanocrystal memory device with HfO/sub 2/ high-k tunneling dielectric

2003 ◽  
Vol 50 (10) ◽  
pp. 2067-2072 ◽  
Author(s):  
Jong Jin Lee ◽  
Xuguang Wang ◽  
Weiping Bai ◽  
Nan Lu ◽  
Dim-Lee Kwong
Keyword(s):  
Experimental Investigation ◽  
Memory Device ◽  
High K ◽  
Si Nanocrystal ◽  
Nanocrystal Memory

Influence of Channel Depletion on the Carrier Charging Characteristics in Si Nanocrystal Floating Gate Memory

2000 ◽  
Vol 39 (Part 1, No. 3A) ◽  
pp. 989-993 ◽  
Author(s):  
Ryuji Ohba ◽  
Naoharu Sugiyama ◽  
Junji Koga ◽  
Ken Uchida ◽  
Akira Toriumi
Keyword(s):  
Floating Gate ◽  
Floating Gate Memory ◽  
Si Nanocrystal

Improvement of Bottom Oxide Thickness Scaling of Inter-Poly Dielectric by Floating Gate Top Plasma Nitridation

2014 ◽  
Vol 35 (2) ◽  
pp. 190-192
Author(s):  
Zih-Song Wang ◽  
Wei-Shiang Huang ◽  
Chih-Yuan Chen ◽  
Hideki Arakawa ◽  
Chrong Jung Lin
Keyword(s):  
Oxide Thickness ◽  
Floating Gate ◽  
Plasma Nitridation
Sign in / Sign up

Export Citation Format

Share Document