Simultaneous voltage scaling and gate sizing for low-power design

Chunhong Chen; M. Sarrafzadeh

doi:10.1109/tcsii.2002.802964

Simultaneous voltage scaling and gate sizing for low-power design

IEEE Transactions on Circuits and Systems II Analog and Digital Signal Processing ◽

10.1109/tcsii.2002.802964 ◽

2002 ◽

Vol 49 (6) ◽

pp. 400-408 ◽

Cited By ~ 20

Author(s):

Chunhong Chen ◽

M. Sarrafzadeh

Keyword(s):

Low Power ◽

Low Power Design ◽

Voltage Scaling ◽

Gate Sizing

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Clustered voltage scaling technique for low-power design

Proceedings of the 1995 international symposium on Low power design - ISLPED '95 ◽

10.1145/224081.224083 ◽

1995 ◽

Cited By ~ 260

Author(s):

Kimiyoshi Usami ◽

Mark Horowitz

Keyword(s):

Low Power ◽

Low Power Design ◽

Voltage Scaling ◽

Scaling Technique

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Extended dynamic voltage scaling for low power design

IEEE International SOC Conference, 2004. Proceedings. ◽

10.1109/socc.2004.1362475 ◽

2004 ◽

Author(s):

Bo Zhai ◽

D. Blaauw ◽

D. Sylvester ◽

K. Flautner

Keyword(s):

Low Power ◽

Low Power Design ◽

Voltage Scaling ◽

Dynamic Voltage Scaling ◽

Dynamic Voltage ◽

Extended Dynamic

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Useful-skew clock routing with gate sizing for low power design

33rd Design Automation Conference Proceedings, 1996 ◽

10.1145/240518.240592 ◽

1996 ◽

Cited By ~ 5

Author(s):

Joe G. Xi ◽

Wayne W.-M. Dai

Keyword(s):

Low Power ◽

Low Power Design ◽

Gate Sizing ◽

Clock Routing

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Variations-Aware Low-Power Design and Block Clustering With Voltage Scaling

IEEE Transactions on Very Large Scale Integration (VLSI) Systems ◽

10.1109/tvlsi.2007.899226 ◽

2007 ◽

Vol 15 (7) ◽

pp. 746-757 ◽

Cited By ~ 3

Author(s):

N. Azizi ◽

M.M. Khellah ◽

V.K. De ◽

F.N. Najm

Keyword(s):

Low Power ◽

Low Power Design ◽

Voltage Scaling ◽

Block Clustering

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Switching-activity driven gate sizing and vth assignment for low power design

Asia and South Pacific Conference on Design Automation, 2006. ◽

10.1109/aspdac.2006.1594747 ◽

2006 ◽

Author(s):

Yu-Hui Huang ◽

Po-Yuan Chen ◽

TingTing Hwang

Keyword(s):

Low Power ◽

Low Power Design ◽

Gate Sizing ◽

Switching Activity

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Variations-aware low-power design with voltage scaling

Proceedings. 42nd Design Automation Conference, 2005. ◽

10.1145/1065579.1065717 ◽

2005 ◽

Cited By ~ 14

Author(s):

Navid Azizi ◽

Muhammad M. Khellah ◽

Vivek De ◽

Farid N. Najm

Keyword(s):

Low Power ◽

Low Power Design ◽

Voltage Scaling

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Variations-aware low-power design with voltage scaling

Proceedings. 42nd Design Automation Conference, 2005. ◽

10.1109/dac.2005.193866 ◽

2005 ◽

Cited By ~ 2

Author(s):

N. Azizi ◽

M.M. Khellah ◽

V. De ◽

F.N. Najm

Keyword(s):

Low Power ◽

Low Power Design ◽

Voltage Scaling

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Comparative evaluation of Body Biasing and Voltage Scaling for Low-Power Design on 28nm UTBB FD-SOI Technology

2019 IEEE/ACM International Symposium on Low Power Electronics and Design (ISLPED) ◽

10.1109/islped.2019.8824791 ◽

2019 ◽

Author(s):

Ricardo Gomez Gomez ◽

Edwige Bano ◽

Sylvain Clerc

Keyword(s):

Low Power ◽

Comparative Evaluation ◽

Low Power Design ◽

Voltage Scaling ◽

Body Biasing ◽

Soi Technology

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Useful-skew clock routing with gate sizing for low power design

33rd Design Automation Conference Proceedings, 1996 ◽

10.1109/dac.1996.545606 ◽

2005 ◽

Cited By ~ 16

Author(s):

J.G. Xi ◽

W.W.-M. Dai

Keyword(s):

Low Power ◽

Low Power Design ◽

Gate Sizing ◽

Clock Routing

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Gate sizing for low power design

IFIP Advances in Information and Communication Technology - SOC Design Methodologies ◽

10.1007/978-0-387-35597-9_26 ◽

2002 ◽

pp. 301-312

Author(s):

Philippe Maurine ◽

Nadine Azemard ◽

Daniel Auvergne

Keyword(s):

Low Power ◽

Low Power Design ◽

Gate Sizing

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