Useful-skew clock routing with gate sizing for low power design

33rd Design Automation Conference Proceedings, 1996 ◽

10.1109/dac.1996.545606 ◽

2005 ◽

Cited By ~ 16

Author(s):

J.G. Xi ◽

W.W.-M. Dai

Keyword(s):

Low Power ◽

Low Power Design ◽

Gate Sizing ◽

Clock Routing

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Useful-skew clock routing with gate sizing for low power design

33rd Design Automation Conference Proceedings, 1996 ◽

10.1145/240518.240592 ◽

1996 ◽

Cited By ~ 5

Author(s):

Joe G. Xi ◽

Wayne W.-M. Dai

Keyword(s):

Low Power ◽

Low Power Design ◽

Gate Sizing ◽

Clock Routing

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Useful-Skew Clock Routing with Gate Sizing for Low Power Design

High Performance Clock Distribution Networks ◽

10.1007/978-1-4684-8440-3_5 ◽

1997 ◽

pp. 51-67

Author(s):

Joe Gufeng Xi ◽

Wayne Wei-Ming Dai

Keyword(s):

Low Power ◽

Low Power Design ◽

Gate Sizing ◽

Clock Routing

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Simultaneous voltage scaling and gate sizing for low-power design

IEEE Transactions on Circuits and Systems II Analog and Digital Signal Processing ◽

10.1109/tcsii.2002.802964 ◽

2002 ◽

Vol 49 (6) ◽

pp. 400-408 ◽

Cited By ~ 20

Author(s):

Chunhong Chen ◽

M. Sarrafzadeh

Keyword(s):

Low Power ◽

Low Power Design ◽

Voltage Scaling ◽

Gate Sizing

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Switching-activity driven gate sizing and vth assignment for low power design

Asia and South Pacific Conference on Design Automation, 2006. ◽

10.1109/aspdac.2006.1594747 ◽

2006 ◽

Author(s):

Yu-Hui Huang ◽

Po-Yuan Chen ◽

TingTing Hwang

Keyword(s):

Low Power ◽

Low Power Design ◽

Gate Sizing ◽

Switching Activity

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Gate sizing for low power design

IFIP Advances in Information and Communication Technology - SOC Design Methodologies ◽

10.1007/978-0-387-35597-9_26 ◽

2002 ◽

pp. 301-312

Author(s):

Philippe Maurine ◽

Nadine Azemard ◽

Daniel Auvergne

Keyword(s):

Low Power ◽

Low Power Design ◽

Gate Sizing

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Switching-activity driven gate sizing and Vth assignment for low power design

Asia and South Pacific Conference on Design Automation, 2006. ◽

10.1145/1118299.1118436 ◽

2006 ◽

Cited By ~ 2

Author(s):

Yu-Hui Huang ◽

Po-Yuan Chen ◽

TingTing Hwang

Keyword(s):

Low Power ◽

Low Power Design ◽

Gate Sizing ◽

Switching Activity

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Power mad [low-power design]

Power Engineering Journal ◽

10.1049/pe:20040307 ◽

2004 ◽

Vol 18 (3) ◽

pp. 37

Author(s):

J. Frenkil

Keyword(s):

Low Power ◽

Low Power Design

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LOW POWER DESIGN FOR TESTABILITY IMPLEMENTATION FOR ASYNCHRONOUS FIFO

i-manager’s Journal on Electronics Engineering ◽

10.26634/jele.9.2.15142 ◽

2019 ◽

Vol 9 (2) ◽

pp. 24

Author(s):

KUMAR PATNALA MADHU ◽

R. NAGENDRA ◽

◽

Keyword(s):

Low Power ◽

Low Power Design ◽

Design For Testability

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An Ultra-Low-Power Design of Smart Wearable Stereo Camera

SoutheastCon 2021 ◽

10.1109/southeastcon45413.2021.9401833 ◽

2021 ◽

Author(s):

Ernesto Sola-Thomas ◽

Masudul Haider Imtiaz

Keyword(s):

Low Power ◽

Low Power Design ◽

Ultra Low Power ◽

Stereo Camera ◽

Smart Wearable

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Low power design challenges for the decade (invited talk)

Proceedings of the 2001 conference on Asia South Pacific design automation - ASP-DAC '01 ◽

10.1145/370155.370356 ◽

2001 ◽

Cited By ~ 17

Author(s):

Shekhar Borkar

Keyword(s):

Low Power ◽

Low Power Design ◽

Design Challenges

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