IFIP Advances in Information and Communication Technology - SOC Design Methodologies
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Published By Springer US

9781475765304, 9780387355979

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Erratum to: SOC Design Methodologies

IFIP Advances in Information and Communication Technology - SOC Design Methodologies ◽

10.1007/978-0-387-35597-9_40 ◽

2017 ◽

pp. E1-E1

Author(s):

Michel Robert ◽

Bruno Rouzeyre ◽

Christian Piguet ◽

Marie-Lise Flottes

Keyword(s):

Design Methodologies

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An Industrial Approach to Core-Based System Chip Testing

IFIP Advances in Information and Communication Technology - SOC Design Methodologies ◽

10.1007/978-0-387-35597-9_33 ◽

2002 ◽

pp. 389-400 ◽

Cited By ~ 1

Author(s):

Erik Jan Marinissen

Keyword(s):

Chip Testing

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Power Consumption Model for the DSP OAK Processor

IFIP Advances in Information and Communication Technology - SOC Design Methodologies ◽

10.1007/978-0-387-35597-9_19 ◽

2002 ◽

pp. 217-228 ◽

Cited By ~ 1

Author(s):

Guitton-Ouhamou Patricia ◽

Belleudy Cécile ◽

Auguin Michel

Keyword(s):

Power Consumption ◽

Consumption Model

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A New Efficient VLSI Architecture for Full Search Block Matching Motion Estimation

IFIP Advances in Information and Communication Technology - SOC Design Methodologies ◽

10.1007/978-0-387-35597-9_22 ◽

2002 ◽

pp. 253-264 ◽

Cited By ~ 3

Author(s):

Nuno Roma ◽

Leonel Sousa

Keyword(s):

Motion Estimation ◽

Vlsi Architecture ◽

Block Matching ◽

Full Search

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Design of a Branch-Based Carry-Select Adder IP Portable in 0.25 µm Bulk and Silicon-On-Insulator CMOS Technologies

IFIP Advances in Information and Communication Technology - SOC Design Methodologies ◽

10.1007/978-0-387-35597-9_15 ◽

2002 ◽

pp. 169-180

Author(s):

Amaury Nève ◽

Denis Flandre

Keyword(s):

Silicon On Insulator ◽

Carry Select Adder

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An Evolutionary Approach for Pareto-optimal Configurations in SOC Platforms

IFIP Advances in Information and Communication Technology - SOC Design Methodologies ◽

10.1007/978-0-387-35597-9_14 ◽

2002 ◽

pp. 157-168 ◽

Cited By ~ 5

Author(s):

Giuseppe Ascia ◽

Vincenzo Catania ◽

Maurizio Palesi

Keyword(s):

Evolutionary Approach ◽

Pareto Optimal ◽

Optimal Configurations

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Power-constrained Test Scheduling for SoCs under a “no session” scheme

IFIP Advances in Information and Communication Technology - SOC Design Methodologies ◽

10.1007/978-0-387-35597-9_34 ◽

2002 ◽

pp. 401-412 ◽

Cited By ~ 3

Author(s):

Marie-Lise Flottes ◽

Julien Pouget ◽

Bruno Rouzeyre

Keyword(s):

Test Scheduling

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A Standardized Co-simulation Backbone

IFIP Advances in Information and Communication Technology - SOC Design Methodologies ◽

10.1007/978-0-387-35597-9_16 ◽

2002 ◽

pp. 181-192 ◽

Cited By ~ 8

Author(s):

Braulio Adriano de Mello ◽

Flávio Rech Wagner

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Dynamically Reconfigurable Architectures for Digital Signal Processing Applications

IFIP Advances in Information and Communication Technology - SOC Design Methodologies ◽

10.1007/978-0-387-35597-9_6 ◽

2002 ◽

pp. 63-74 ◽

Cited By ~ 2

Author(s):

Gilles Sassatelli ◽

Lionel Torres ◽

Pascal Benoit ◽

Gaston Cambon ◽

Michel Robert ◽

...

Keyword(s):

Signal Processing ◽

Digital Signal Processing ◽

Digital Signal ◽

Reconfigurable Architectures ◽

Dynamically Reconfigurable

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Interconnect Capacitance Modelling in a VDSM CMOS Technology

IFIP Advances in Information and Communication Technology - SOC Design Methodologies ◽

10.1007/978-0-387-35597-9_12 ◽

2002 ◽

pp. 133-144 ◽

Cited By ~ 1

Author(s):

David Bernard ◽

Christian Landrault ◽

Pascal Nouet

Keyword(s):

Cmos Technology

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IFIP Advances in Information and Communication Technology - SOC Design MethodologiesLatest Publications

TOTAL DOCUMENTS

H-INDEX

Published By Springer US

Erratum to: SOC Design Methodologies

An Industrial Approach to Core-Based System Chip Testing

Power Consumption Model for the DSP OAK Processor

A New Efficient VLSI Architecture for Full Search Block Matching Motion Estimation

Design of a Branch-Based Carry-Select Adder IP Portable in 0.25 µm Bulk and Silicon-On-Insulator CMOS Technologies

An Evolutionary Approach for Pareto-optimal Configurations in SOC Platforms

Power-constrained Test Scheduling for SoCs under a “no session” scheme

A Standardized Co-simulation Backbone

Dynamically Reconfigurable Architectures for Digital Signal Processing Applications

Interconnect Capacitance Modelling in a VDSM CMOS Technology

IFIP Advances in Information and Communication Technology - SOC Design Methodologies
Latest Publications