Variations-aware low-power design with voltage scaling

Proceedings. 42nd Design Automation Conference, 2005. ◽

10.1109/dac.2005.193866 ◽

2005 ◽

Cited By ~ 2

Author(s):

N. Azizi ◽

M.M. Khellah ◽

V. De ◽

F.N. Najm

Keyword(s):

Low Power ◽

Low Power Design ◽

Voltage Scaling

Download Full-text

Clustered voltage scaling technique for low-power design

Proceedings of the 1995 international symposium on Low power design - ISLPED '95 ◽

10.1145/224081.224083 ◽

1995 ◽

Cited By ~ 260

Author(s):

Kimiyoshi Usami ◽

Mark Horowitz

Keyword(s):

Low Power ◽

Low Power Design ◽

Voltage Scaling ◽

Scaling Technique

Download Full-text

Extended dynamic voltage scaling for low power design

IEEE International SOC Conference, 2004. Proceedings. ◽

10.1109/socc.2004.1362475 ◽

2004 ◽

Author(s):

Bo Zhai ◽

D. Blaauw ◽

D. Sylvester ◽

K. Flautner

Keyword(s):

Low Power ◽

Low Power Design ◽

Voltage Scaling ◽

Dynamic Voltage Scaling ◽

Dynamic Voltage ◽

Extended Dynamic

Download Full-text

Simultaneous voltage scaling and gate sizing for low-power design

IEEE Transactions on Circuits and Systems II Analog and Digital Signal Processing ◽

10.1109/tcsii.2002.802964 ◽

2002 ◽

Vol 49 (6) ◽

pp. 400-408 ◽

Cited By ~ 20

Author(s):

Chunhong Chen ◽

M. Sarrafzadeh

Keyword(s):

Low Power ◽

Low Power Design ◽

Voltage Scaling ◽

Gate Sizing

Download Full-text

Variations-Aware Low-Power Design and Block Clustering With Voltage Scaling

IEEE Transactions on Very Large Scale Integration (VLSI) Systems ◽

10.1109/tvlsi.2007.899226 ◽

2007 ◽

Vol 15 (7) ◽

pp. 746-757 ◽

Cited By ~ 3

Author(s):

N. Azizi ◽

M.M. Khellah ◽

V.K. De ◽

F.N. Najm

Keyword(s):

Low Power ◽

Low Power Design ◽

Voltage Scaling ◽

Block Clustering

Download Full-text

Variations-aware low-power design with voltage scaling

Proceedings. 42nd Design Automation Conference, 2005. ◽

10.1145/1065579.1065717 ◽

2005 ◽

Cited By ~ 14

Author(s):

Navid Azizi ◽

Muhammad M. Khellah ◽

Vivek De ◽

Farid N. Najm

Keyword(s):

Low Power ◽

Low Power Design ◽

Voltage Scaling

Download Full-text

Comparative evaluation of Body Biasing and Voltage Scaling for Low-Power Design on 28nm UTBB FD-SOI Technology

2019 IEEE/ACM International Symposium on Low Power Electronics and Design (ISLPED) ◽

10.1109/islped.2019.8824791 ◽

2019 ◽

Author(s):

Ricardo Gomez Gomez ◽

Edwige Bano ◽

Sylvain Clerc

Keyword(s):

Low Power ◽

Comparative Evaluation ◽

Low Power Design ◽

Voltage Scaling ◽

Body Biasing ◽

Soi Technology

Download Full-text

Gate-level voltage scaling for low-power design using multiple supply voltages

IEE Proceedings - Circuits Devices and Systems ◽

10.1049/ip-cds:19990579 ◽

1999 ◽

Vol 146 (6) ◽

pp. 334 ◽

Cited By ~ 5

Author(s):

C. Yeh ◽

M.-C. Chang

Keyword(s):

Low Power ◽

Low Power Design ◽

Voltage Scaling ◽

Supply Voltages ◽

Multiple Supply Voltages

Download Full-text

A top-down low power design technique using clustered voltage scaling with variable supply-voltage scheme

Proceedings of the IEEE 1998 Custom Integrated Circuits Conference (Cat. No.98CH36143) ◽

10.1109/cicc.1998.695026 ◽

2002 ◽

Cited By ~ 50

Author(s):

M. Hamada ◽

M. Takahashi ◽

H. Arakida ◽

A. Chiba ◽

T. Terazawa ◽

...

Keyword(s):

Low Power ◽

Supply Voltage ◽

Low Power Design ◽

Voltage Scaling ◽

Design Technique ◽

Top Down ◽

Down Low

Download Full-text

Power mad [low-power design]

Power Engineering Journal ◽

10.1049/pe:20040307 ◽

2004 ◽

Vol 18 (3) ◽

pp. 37

Author(s):

J. Frenkil

Keyword(s):

Low Power ◽

Low Power Design

Download Full-text

LOW POWER DESIGN FOR TESTABILITY IMPLEMENTATION FOR ASYNCHRONOUS FIFO

i-manager’s Journal on Electronics Engineering ◽

10.26634/jele.9.2.15142 ◽

2019 ◽

Vol 9 (2) ◽

pp. 24

Author(s):

KUMAR PATNALA MADHU ◽

R. NAGENDRA ◽

◽

Keyword(s):

Low Power ◽

Low Power Design ◽

Design For Testability

Download Full-text