Design of hierarchical cellular automata for on-chip test pattern generator

2002 ◽  
Vol 21 (12) ◽  
pp. 1530-1539 ◽  
Author(s):  
B.K. Sikdar ◽  
N. Ganguly ◽  
P.P. Chaudhuri
Keyword(s):  
Cellular Automata ◽  
Test Pattern ◽  
Pattern Generator ◽  
On Chip

Hierarchical cellular automata as an on-chip test pattern generator

2002 ◽  
Author(s):  
B.K. Sikdar ◽  
P. Majumder ◽  
M. Mukherjee ◽  
N. Ganguly ◽  
D.K. Das ◽  
...  
Keyword(s):  
Cellular Automata ◽  
Test Pattern ◽  
Pattern Generator ◽  
On Chip

Weighted Cellular Automata Design for Test Pattern Generator Based on Genetic Algorithm

2013 ◽  
Vol 273 ◽  
pp. 840-844 ◽  
Author(s):  
En Min Tan ◽  
Qing Qing Li ◽  
Ji Gang Jiang
Keyword(s):  
Cellular Automata ◽  
Test Pattern ◽  
Pattern Generator ◽  
Fault Coverage ◽  
Test Design ◽  
Design For Test ◽  
Test Length ◽  
Vlsi Test ◽  
Self Test ◽  
Built In Self Test

In built-in self-test design for VLSI, test pattern generator should satisfy some multi-targets, such as test length, fault coverage and test consumption, etc. A one-dimension hybrid cellular automata (CA) is used as the core of test pattern generator, with an optimization of its rules based on multi-objectives evolution algorithm. A certain rule which selected from the optimized rule set is adopted to form the weighted cellular automata, by the using of verilog HDL. Experiment results was obtained by simulation of some ISCAS’8n built-in self-test design for VLSI, test pattern generator should satisfy some multi-targets, such as test le5 benchmark circuits, and indicated that the test length was reduced obviously (at a ratio above 60%), without losing fault coverage (within a discrepancy of 3%); moreover, the power consumption would be decreased correspondingly.

scholarly journals New Structure of Test Pattern Generator Stimulating Crosstalks in Bus-type Connections

2015 ◽  
Vol 61 (1) ◽  
pp. 67-75
Author(s):  
Tomasz Garbolino
Keyword(s):  
Test Pattern ◽  
Pattern Generator ◽  
System On Chip ◽  
Hardware Description Language ◽  
Test Sequence ◽  
Description Language ◽  
Hardware Description ◽  
Parameterized Model ◽  
On Chip ◽  
Operation Frequency

Abstract The paper discloses the idea of a new structure for a Test Pattern Generator (TPG) for detection of crosstalk faults that may happen to bus-type interconnections between built-in blocks within a System-on-Chip structure. The new idea is an improvement of the TPG design proposed by the author in one of the previous studies. The TPG circuit is meant to generate test sequences that guarantee detection of all crosstalk faults with the capacitive nature that may occur between individual lines within an interconnecting bus. The study comprises a synthesizable and parameterized model developed for the presented TPG in the VLSI Hardware Description Language (VHDL) with further investigation of properties and features of the offered module. The significant advantages of the proposed TPG structure include less area occupied on a chip and higher operation frequency as compared to other solutions. In addition, the design demonstrates good scalability in terms of both the hardware overhead and the length of the generated test sequence

Sign in / Sign up

Export Citation Format

Share Document