2005 IEEE VLSI-TSA International Symposium on VLSI Design, Automation and Test, 2005. (VLSI-TSA-DAT).
Latest Publications

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Published By IEEE

0780390601

Latest Documents Most Cited Documents Contributed Authors Related Sources Related Keywords

Implementation of dynamically reconfigurable processor DAPDNA-2

2005 IEEE VLSI-TSA International Symposium on VLSI Design, Automation and Test, 2005. (VLSI-TSA-DAT). ◽

10.1109/vdat.2005.1500086 ◽

2005 ◽

Cited By ~ 21

Author(s):

T. Sato ◽

H. Watanabe ◽

K. Shiba

Keyword(s):

Reconfigurable Processor ◽

Dynamically Reconfigurable

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A novel register organization for VLIW digital signal processors

2005 IEEE VLSI-TSA International Symposium on VLSI Design, Automation and Test, 2005. (VLSI-TSA-DAT). ◽

10.1109/vdat.2005.1500090 ◽

2005 ◽

Author(s):

Tay-Jyi Lin ◽

Chen-Chia Lee ◽

Chih-Wei Liu ◽

Chein-Wei Jen

Keyword(s):

Digital Signal ◽

Digital Signal Processors ◽

Signal Processors

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Low-power BIBITS encoding with register relabeling for instruction bus

2005 IEEE VLSI-TSA International Symposium on VLSI Design, Automation and Test, 2005. (VLSI-TSA-DAT). ◽

10.1109/vdat.2005.1500015 ◽

2005 ◽

Cited By ~ 1

Author(s):

Chin-Tzung Cheng ◽

Wei-Hau Chiao ◽

Jean Jyh-Jiun Shann ◽

Chung-Ping Chung ◽

Wen-Feng Chen

Keyword(s):

Low Power

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Dual-block-pipelined VLSI architecture of entropy coding for H.264/AVC baseline profile

2005 IEEE VLSI-TSA International Symposium on VLSI Design, Automation and Test, 2005. (VLSI-TSA-DAT). ◽

10.1109/vdat.2005.1500073 ◽

2005 ◽

Cited By ~ 15

Author(s):

Tung-Chien Chen ◽

Yu-Wen Huang ◽

Chuan-Yong Tsai ◽

Bing-Yu Hsieh ◽

Liang-Gee Chen

Keyword(s):

Vlsi Architecture ◽

Entropy Coding

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Embedded memory diagnostic data compression using differential address

2005 IEEE VLSI-TSA International Symposium on VLSI Design, Automation and Test, 2005. (VLSI-TSA-DAT). ◽

10.1109/vdat.2005.1500009 ◽

2005 ◽

Author(s):

Chin-Lung Su ◽

Rei-Fu Huang ◽

Cheng-Wen Wu ◽

Yeong-Jar Chang ◽

Shen-Tien Lin ◽

...

Keyword(s):

Data Compression ◽

Embedded Memory ◽

Diagnostic Data

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A 1.25Gb/s half-rate clock and data recovery circuit

2005 IEEE VLSI-TSA International Symposium on VLSI Design, Automation and Test, 2005. (VLSI-TSA-DAT). ◽

10.1109/vdat.2005.1500033 ◽

2005 ◽

Cited By ~ 1

Author(s):

Ching-Yuan Yan ◽

Cheng-Hsing Lee ◽

Yu Lee

Keyword(s):

Clock And Data Recovery ◽

Data Recovery

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A 1.6-GHz delta-sigma modulated fractional-N frequency synthesizer

2005 IEEE VLSI-TSA International Symposium on VLSI Design, Automation and Test, 2005. (VLSI-TSA-DAT). ◽

10.1109/vdat.2005.1500044 ◽

2005 ◽

Author(s):

Ching-Yuan Yang ◽

Kuei-Zu Jiang ◽

Jen-Wen Chen

Keyword(s):

Frequency Synthesizer ◽

Delta Sigma

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Parahel core testing with multiple scan chains by test vector overlapping

2005 IEEE VLSI-TSA International Symposium on VLSI Design, Automation and Test, 2005. (VLSI-TSA-DAT). ◽

10.1109/vdat.2005.1500056 ◽

2005 ◽

Cited By ~ 1

Author(s):

T. Shinogi ◽

Y. Yamada ◽

T. Hayashi ◽

T. Yoshikawa ◽

S. Tsuruoka

Keyword(s):

Test Vector ◽

Multiple Scan ◽

Scan Chains

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A hardware/software-concurrent JPEG2000 encoder

2005 IEEE VLSI-TSA International Symposium on VLSI Design, Automation and Test, 2005. (VLSI-TSA-DAT). ◽

10.1109/vdat.2005.1500050 ◽

2005 ◽

Author(s):

Wen-Chi Yen ◽

An-Chi Chen ◽

Po-Sheng Liu ◽

Yom-Long Lin

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Buffered tree refinement considering timing and congestion

2005 IEEE VLSI-TSA International Symposium on VLSI Design, Automation and Test, 2005. (VLSI-TSA-DAT). ◽

10.1109/vdat.2005.1500021 ◽

2005 ◽

Author(s):

Wei-Zhi Ye ◽

Ting-Chi Wang

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2005 IEEE VLSI-TSA International Symposium on VLSI Design, Automation and Test, 2005. (VLSI-TSA-DAT).Latest Publications

TOTAL DOCUMENTS

H-INDEX

Published By IEEE

Implementation of dynamically reconfigurable processor DAPDNA-2

A novel register organization for VLIW digital signal processors

Low-power BIBITS encoding with register relabeling for instruction bus

Dual-block-pipelined VLSI architecture of entropy coding for H.264/AVC baseline profile

Embedded memory diagnostic data compression using differential address

A 1.25Gb/s half-rate clock and data recovery circuit

A 1.6-GHz delta-sigma modulated fractional-N frequency synthesizer

Parahel core testing with multiple scan chains by test vector overlapping

A hardware/software-concurrent JPEG2000 encoder

Buffered tree refinement considering timing and congestion

2005 IEEE VLSI-TSA International Symposium on VLSI Design, Automation and Test, 2005. (VLSI-TSA-DAT).
Latest Publications