Design of an on-chip test pattern generator without prohibited pattern set (PPS)

2003 ◽  
Author(s):  
N. Ganguly ◽  
B.K. Sikdar ◽  
P.P. Chaudhuri
Keyword(s):  
Test Pattern ◽  
Pattern Generator ◽  
On Chip

scholarly journals New Structure of Test Pattern Generator Stimulating Crosstalks in Bus-type Connections

2015 ◽  
Vol 61 (1) ◽  
pp. 67-75
Author(s):  
Tomasz Garbolino
Keyword(s):  
Test Pattern ◽  
Pattern Generator ◽  
System On Chip ◽  
Hardware Description Language ◽  
Test Sequence ◽  
Description Language ◽  
Hardware Description ◽  
Parameterized Model ◽  
On Chip ◽  
Operation Frequency

Abstract The paper discloses the idea of a new structure for a Test Pattern Generator (TPG) for detection of crosstalk faults that may happen to bus-type interconnections between built-in blocks within a System-on-Chip structure. The new idea is an improvement of the TPG design proposed by the author in one of the previous studies. The TPG circuit is meant to generate test sequences that guarantee detection of all crosstalk faults with the capacitive nature that may occur between individual lines within an interconnecting bus. The study comprises a synthesizable and parameterized model developed for the presented TPG in the VLSI Hardware Description Language (VHDL) with further investigation of properties and features of the offered module. The significant advantages of the proposed TPG structure include less area occupied on a chip and higher operation frequency as compared to other solutions. In addition, the design demonstrates good scalability in terms of both the hardware overhead and the length of the generated test sequence

Hierarchical cellular automata as an on-chip test pattern generator

2002 ◽  
Author(s):  
B.K. Sikdar ◽  
P. Majumder ◽  
M. Mukherjee ◽  
N. Ganguly ◽  
D.K. Das ◽  
...  
Keyword(s):  
Cellular Automata ◽  
Test Pattern ◽  
Pattern Generator ◽  
On Chip

TESTING OF SOC INTERCONNECTS USING EXTENDED IEEE 1500 STANDARD

2012 ◽  
Vol 21 (05) ◽  
pp. 1250036
Author(s):  
NAFISEH MOUSAVIAN ◽  
REZA NOURMANDI-POUR ◽  
ARASH GHORBANNIA-DELAVAR
Keyword(s):  
Model Test ◽  
Test Pattern ◽  
Pattern Generator ◽  
System On Chip ◽  
Test Model ◽  
Speed Test ◽  
Serial Test ◽  
Test Access Mechanism ◽  
On Chip

In this paper, we proposed BIST-based architecture to at-speed test of crosstalk faults for system-on-chip interconnects. This architecture includes IEEE 1500 wrapper enhanced cells intended for multiple victim test model test patterns generation and analysis test responses. One new instruction is used to control cells and test pattern generator controller in serial test access mechanism of the standard in order to fully comply with conventional IEEE 1500 standard.

Enabling Electro-Optical Failure Analysis within Extreme Compression Test Architecture

2016 ◽  
Author(s):  
Rudolf Schlangen ◽  
Jon Colburn ◽  
Joe Sarmiento ◽  
Bala Tarun Nelapatla ◽  
Puneet Gupta
Keyword(s):  
Failure Analysis ◽  
Compression Test ◽  
Test Pattern ◽  
Pattern Generation ◽  
Output Data ◽  
Test Compression ◽  
Test Loop ◽  
On Chip ◽  
Test Architecture

Abstract Driven by the need for higher test-compression, increasingly many chip-makers are adopting new DFT architectures such as “Extreme-Compression” (XTR, supported by Synopsys) with on-chip pattern generation and MISR based compression of chain output data. This paper discusses test-loop requirements in general and gives Advantest 93k specific guidelines on test-pattern release and ATE setup necessary to enable the most established EFA techniques such as LVP and SDL (aka DLS, LADA) within the XTR test architecture.

Dynamic Photon Emission on FinFET Devices Through Novel Scan Test Approaches

2019 ◽  
Author(s):  
Ranganathan Gopinath ◽  
Ravikumar Venkat Krishnan ◽  
Lua Winson ◽  
Phoa Angeline ◽  
Jin Jie
Keyword(s):  
Test Pattern ◽  
Photon Emission ◽  
Pattern Generator ◽  
Lower Probability ◽  
Automated Test Equipment ◽  
Use Patterns ◽  
Infra Red ◽  
Automatic Test Pattern Generator ◽  
Technology Nodes ◽  
Established Technique

Abstract Dynamic Photon Emission Microscopy (D-PEM) is an established technique for isolating short and open failures, where photons emitted by transistors are collected by sensitive infra-red detectors while the device under test is electrically exercised with automated test equipment (ATE). Common tests, such as scan, use patterns that are generated through Automatic Test Pattern Generator (ATPG) in compressed mode. When these patterns are looped for D-PEM, it results in indeterministic states within cells during the load or unload sequences, making interpretation of emission challenging. Moreover, photons are emitted with lower probability and lesser energies for smaller technology nodes such as the FinFET. In this paper, we will discuss executing scan tests in manners that can be used to bring out emission which did not show up in conventional test loops.

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