A Low Power Deterministic Test Pattern Generator for BIST Based on Cellular Automata

2008 ◽  
Author(s):  
Bei Cao ◽  
Liyi Xiao ◽  
Yongsheng Wang
Keyword(s):  
Cellular Automata ◽  
Low Power ◽  
Test Pattern ◽  
Pattern Generator

Weighted Cellular Automata Design for Test Pattern Generator Based on Genetic Algorithm

2013 ◽  
Vol 273 ◽  
pp. 840-844 ◽  
Author(s):  
En Min Tan ◽  
Qing Qing Li ◽  
Ji Gang Jiang
Keyword(s):  
Cellular Automata ◽  
Test Pattern ◽  
Pattern Generator ◽  
Fault Coverage ◽  
Test Design ◽  
Design For Test ◽  
Test Length ◽  
Vlsi Test ◽  
Self Test ◽  
Built In Self Test

In built-in self-test design for VLSI, test pattern generator should satisfy some multi-targets, such as test length, fault coverage and test consumption, etc. A one-dimension hybrid cellular automata (CA) is used as the core of test pattern generator, with an optimization of its rules based on multi-objectives evolution algorithm. A certain rule which selected from the optimized rule set is adopted to form the weighted cellular automata, by the using of verilog HDL. Experiment results was obtained by simulation of some ISCAS’8n built-in self-test design for VLSI, test pattern generator should satisfy some multi-targets, such as test le5 benchmark circuits, and indicated that the test length was reduced obviously (at a ratio above 60%), without losing fault coverage (within a discrepancy of 3%); moreover, the power consumption would be decreased correspondingly.

A Low Power Test Pattern Generator for BIST

2010 ◽  
Vol E93-C (5) ◽  
pp. 696-702 ◽  
Author(s):  
Shaochong LEI ◽  
Feng LIANG ◽  
Zeye LIU ◽  
Xiaoying WANG ◽  
Zhen WANG
Keyword(s):  
Low Power ◽  
Test Pattern ◽  
Pattern Generator ◽  
Power Test ◽  
Low Power Test

scholarly journals LPTest: a Flexible Low-Power Test Pattern Generator

2009 ◽  
Vol 25 (6) ◽  
pp. 323-335 ◽  
Author(s):  
Meng-Fan Wu ◽  
Kai-Shun Hu ◽  
Jiun-Lang Huang
Keyword(s):  
Low Power ◽  
Test Pattern ◽  
Pattern Generator ◽  
Power Test ◽  
Low Power Test
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