Gm enhancement for bulk-driven sub-threshold differential pair in nanometer CMOS process

2012 ◽  
Author(s):  
Luis H. C. Ferreira ◽  
Sameer R. Sonkusale
Keyword(s):  
Cmos Process ◽  
Nanometer Cmos ◽  
Differential Pair

Leakage Reduction of P-Type Logic Circuits Using Pass-Transistor Adiabatic Logic with PMOS Pull-up Configuration

2010 ◽  
Vol 39 ◽  
pp. 73-78 ◽  
Author(s):  
Jin Tao Jiang ◽  
Li Fang Ye ◽  
Jian Ping Hu
Keyword(s):  
Gate Oxide ◽  
Cmos Process ◽  
Oxide Materials ◽  
Gate Leakage ◽  
Leakage Reduction ◽  
Nanometer Cmos ◽  
Benchmark Circuit ◽  
Adiabatic Logic ◽  
Pass Transistor ◽  
Cmos Processes

Leakage power reduction is extremely important in the design of nano-circuits. Gate leakage has become a significant component in currently used nanometer CMOS processes with gate oxide structure. The structure and operation of the PAL-2P (pass-transistor adiabatic logic with PMOS pull-up configuration) circuits that consist mostly of PMOS transistors are complementary to PAL-2N (pass-transistor adiabatic logic with NMOS pull-down configuration) ones that consist mostly of NMOS transistors. This paper investigates gate leakage reduction of the PAL-2P circuits in nanometer CMOS processes with gate oxide materials. An s27 benchmark circuit from the ISCAS89 sequential benchmark set is verified using the PAL-2P scheme. All circuits are simulated with HSPICE using the 65nm CMOS process with gate oxide materials. Based on the power dissipation models of PAL-2P adiabatic circuits, active leakage dissipations are estimated by testing total leakage dissipations using SPICE simulations. The PAL-2P circuits consume low static power compared with traditional PAL-2N ones.

scholarly journals Chebyshev Bandpass Filter Using Resonator of Tunable Active Capacitor and Inductor

VLSI Design ◽  
2017 ◽  
Vol 2017 ◽  
pp. 1-12 ◽  
Author(s):  
Yu Wang ◽  
Jian Chen ◽  
Chien-In Henry Chen
Keyword(s):  
Bandpass Filter ◽  
Low Cost ◽  
Center Frequency ◽  
Pass Band ◽  
Cmos Process ◽  
Frequency Range ◽  
Active Components ◽  
Fully Integrated ◽  
Nanometer Cmos ◽  
Tuning Frequency

A classic second-order coupled-capacitor Chebyshev bandpass filter using resonator of tunable active capacitor and inductor is presented. The low cost and small size of CMOS active components make the bandpass filter (BPF) attractive in fully integrated CMOS applications. The tunable active capacitor is designed to compensate active inductor’s resistance for resistive match in the resonator. In many design cases, more than 95% resistive loss is cancelled. Meanwhile, adjusting design parameter of the active component provides BPF tunability in center frequency, pass band, and pass band gain. Designed in 1.8 V 180 nanometer CMOS process, the BPF has a tuning frequency range of 758–864 MHz, a controllable pass band of 7.1–65.9 MHz, a quality factor Q of 12–107, a pass band gain of 6.5–18.1 dB, and a stopband rejection of 38–50 dB.

scholarly journals A low power comparator utilizing MTSCStack, DTTS, and bulk-driven techniques

2021 ◽  
Vol 10 (3) ◽  
pp. 221
Author(s):  
Mohd Tafir Mustaffa
Keyword(s):  
Low Power ◽  
High Speed ◽  
Low Voltage ◽  
Promising Result ◽  
Industrial Applications ◽  
Modern Technology ◽  
Total Power ◽  
Cmos Process ◽  
Process Technology ◽  
Differential Pair

Comparator is one of the main blocks that play a vital task in the performance of analog to digital converters (ADC) in all modern technology devices. High-speed devices with low voltage and low power are considered essential for industrial applications. The design of a low-power comparator with high speed is required to accomplish the requirements mostly in electronic devices that are necessary for high-speed ADCs. However, a high-speed device that leads the scaling down of CMOS process technology will consume more power. Thus, power reduction techniques such as multi-threshold super cut-off stack (MTSCStack), dual-threshold transistor stacking (DTTS), a bulk-driven, and a bulk-driven differential pair were studied in this work. This study aims to find and build the combination of these techniques to produce a comparator that can operate in low power without compromising existing performance using the 0.13-µm CMOS process. A comparator with a combination of MTSCStack, DTTS, and NMOS bulk-driven differential pair shows the most promising result of 6.29 µW for static power, 17.15 µW for dynamic power, and 23.44 µW for total power.

Leakage Power Estimation of Adiabatic Circuits Using SPICE in Nanometer CMOS Processes

2010 ◽  
Vol 108-111 ◽  
pp. 625-630 ◽  
Author(s):  
Yang Bo Wu ◽  
Jian Ping Hu ◽  
Hong Li
Keyword(s):  
Significant Proportion ◽  
Power Estimation ◽  
Low Power Design ◽  
Leakage Power ◽  
Cmos Process ◽  
Cmos Circuits ◽  
Nanometer Cmos ◽  
Adiabatic Logic ◽  
Total Leakage ◽  
Pass Transistor

In deep sub-micro CMOS process, the leakage power is becoming a significant proportion in power dissipation. Hence, estimating the leakage power of CMOS circuits is very important in low-power design. In this paper, an estimation technology for the total leakage power of adiabatic logic circuits by using SPICE is proposed. The basic principle of power estimation for traditional CMOS circuits using SPICE is introduced. According to the energy dissipation characteristic of adiabatic circuits, the estimation technology for leakage power is discussed. Taken as an example, the estimation for total leakage power dissipations of PAL-2N (pass-transistor adiabatic logic with NMOS pull-down configuration) circuits is illustrated using the proposed estimation technology.

Technique to improve CMRR at high frequencies in CMOS OTA-C filters

2013 ◽  
Vol 61 (3) ◽  
pp. 697-703
Author(s):  
G. Blakiewicz
Keyword(s):  
Slight Modification ◽  
Cmos Process ◽  
Pass Filter ◽  
Low Pass Filter ◽  
Chip Area ◽  
High Frequencies ◽  
Operational Transconductance Amplifiers ◽  
Low Pass ◽  
Differential Pair ◽  
The Common

Abstract In this paper a technique to improve the common-mode rejection ratio (CMRR) at high frequencies in the OTA-C filters is proposed. The technique is applicable to most OTA-C filters using CMOS operational transconductance amplifiers (OTA) based on differential pairs. The presented analysis shows that a significant broadening of CMRR bandwidth can be achieved by using a differential pair with the bodies of transistors connected to AC ground, instead of using a pair with the bodies connected to the sources. The key advantages of the technique are: no increase in power consumption (except for an optional tuning circuit), a small increase of a chip area, a slight modification of the original filter. The simulation results for exemplary OTAs and a low-pass filter, designed in a 0.35 μm CMOS process, show the possibility of broadening the CMRR bandwidth several times.

Dual Damascene Process for FatWires in Copper/FSG Technology

2003 ◽  
Vol 766 ◽  
Author(s):  
J. Gambino ◽  
T. Stamper ◽  
H. Trombley ◽  
S. Luce ◽  
F. Allen ◽  
...  
Keyword(s):  
Line Width ◽  
Lower Cost ◽  
Process Window ◽  
Cmos Process ◽  
Dual Damascene ◽  
Damascene Process ◽  
Interconnect Technology

AbstractA trench-first dual damascene process has been developed for fat wires (1.26 μm pitch, 1.1 μm thickness) in a 0.18 μm CMOS process with copper/fluorosilicate glass (FSG) interconnect technology. The process window for the patterning of vias in such deep trenches depends on the trench depth and on the line width of the trench, with the worse case being an intermediate line width (lines that are 3X the via diameter). Compared to a single damascene process, the dual damascene process has comparable yield and reliability, with lower via resistance and lower cost.

A 5-bit 4.2-GS/s Flash ADC in 0.13-µm CMOS Process

2009 ◽  
Vol E92-C (2) ◽  
pp. 258-268 ◽  
Author(s):  
Ying-Zu LIN ◽  
Soon-Jyh CHANG ◽  
Yen-Ting LIU
Keyword(s):  
Cmos Process ◽  
Flash Adc
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