The dynamic conductance and transconductance in double-gate (gate-all-round) SOI devices

2000 IEEE International SOI Conference. Proceedings (Cat. No.00CH37125) ◽

10.1109/soi.2000.892797 ◽

2002 ◽

Cited By ~ 1

Author(s):

A. Vandooren ◽

S. Cristoloveanu ◽

J.P. Colinge

Keyword(s):

Double Gate ◽

Soi Devices ◽

Dynamic Conductance

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A low power four transistor Schmitt Trigger for asymmetric double gate fully depleted SOI devices

2003 IEEE International Conference on Robotics and Automation (Cat No 03CH37422) SOI-03) ◽

10.1109/soi.2003.1242882 ◽

2003 ◽

Cited By ~ 18

Author(s):

Cakici ◽

Bansal ◽

Roy

Keyword(s):

Low Power ◽

Schmitt Trigger ◽

Double Gate ◽

Fully Depleted ◽

Soi Devices

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Geometric Magnetoresistance and Mobility Behavior in Single-Gate and Double-Gate SOI Devices

2007 IEEE International SOI Conference ◽

10.1109/soi.2007.4357851 ◽

2007 ◽

Cited By ~ 1

Author(s):

N. Rodriguez ◽

L. Donetti ◽

F. Gamiz ◽

S. Cristoloveanu

Keyword(s):

Double Gate ◽

Mobility Behavior ◽

Soi Devices

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Double-gate SOI devices for low-power and high-performance applications

19th International Conference on VLSI Design held jointly with 5th International Conference on Embedded Systems Design (VLSID'06) ◽

10.1109/vlsid.2006.74 ◽

2006 ◽

Cited By ~ 6

Author(s):

K. Roy ◽

H. Mahmoodi ◽

S. Mukhopadhyay ◽

H. Ananthan ◽

A. Bansal ◽

...

Keyword(s):

Low Power ◽

High Performance ◽

Double Gate ◽

Soi Devices

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Preparation of 200 mm silicon substrates with metal ground-plane for double-gate SOI devices

2000 IEEE International SOI Conference. Proceedings (Cat. No.00CH37125) ◽

10.1109/soi.2000.892746 ◽

2002 ◽

Cited By ~ 1

Author(s):

L.J. Huang ◽

K. Chan ◽

P.M. Solomon ◽

E. Jones ◽

C. D'Emic ◽

...

Keyword(s):

Ground Plane ◽

Silicon Substrates ◽

Double Gate ◽

Soi Devices

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Double-gate SOI devices for low-power and high-performance applications

ICCAD-2005. IEEE/ACM International Conference on Computer-Aided Design, 2005. ◽

10.1109/iccad.2005.1560067 ◽

2005 ◽

Cited By ~ 14

Author(s):

K. Roy ◽

H. Mahmoodi ◽

S. Mukhopadhyay ◽

H. Ananthan ◽

A. Bansal ◽

...

Keyword(s):

Low Power ◽

High Performance ◽

Double Gate ◽

Soi Devices

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Two-dimensional modeling of quantum ballistic transport in ultimate double-gate SOI devices

Solid-State Electronics ◽

10.1016/s0038-1101(03)00039-x ◽

2003 ◽

Vol 47 (7) ◽

pp. 1219-1225 ◽

Cited By ~ 58

Author(s):

D. Munteanu ◽

J.L. Autran

Keyword(s):

Ballistic Transport ◽

Double Gate ◽

Two Dimensional ◽

Dimensional Modeling ◽

Soi Devices ◽

Quantum Ballistic Transport

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Monte-Carlo Simulation of Decananometric Double-Gate SOI devices: Multi-Subband vs. 3D-Electron Gas with Quantum Corrections

2006 European Solid-State Device Research Conference ◽

10.1109/essder.2006.307663 ◽

2006 ◽

Cited By ~ 9

Author(s):

I. Riolino ◽

M. Braccioli ◽

L. Lucci ◽

D. Esseni ◽

C. Fiegna ◽

...

Keyword(s):

Monte Carlo Simulation ◽

Monte Carlo ◽

Electron Gas ◽

Quantum Corrections ◽

Double Gate ◽

Soi Devices ◽

3D Electron

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Linearity Analysis in Double Gate Graded-Channel Soi Devices Applied to 2-Mos Mosfet-C Balanced Structures

ECS Transactions ◽

10.1149/1.2956041 ◽

2019 ◽

Vol 14 (1) ◽

pp. 273-282

Author(s):

Rodrigo T. Doria ◽

Antonio Cerdeira ◽

Jean-Pierre Raskin ◽

Denis Flandre ◽

Marcelo A. Pavanello

Keyword(s):

Double Gate ◽

Soi Devices

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To study high performance analysis of surround gate SOI MOSFET

International Journal of Engineering & Technology ◽

10.14419/ijet.v7i2.8.10405 ◽

2018 ◽

Vol 7 (2.8) ◽

pp. 191

Author(s):

Arjimand Ashaf ◽

Manisha Tyagi ◽

Prashant Mani

Keyword(s):

Performance Analysis ◽

High Performance ◽

Device Modeling ◽

Double Gate ◽

Electrical Characteristics ◽

Soi Mosfet ◽

Gate Structure ◽

Rigorous Study ◽

Soi Devices

In this paper, we are presenting a rigorous study about SOI MOSFET devices development. The development of SOI devices based on gate structure from single gate to surround gate is presented in this paper. We compared the various electrical characteristics between Single gate, double gate, and bulk and also discussed the device modeling based on surround gate structure.

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Hole Mobility in Ultrathin Double-Gate SOI Devices: The Effect of Acoustic Phonon Confinement

IEEE Electron Device Letters ◽

10.1109/led.2009.2032568 ◽

2009 ◽

Vol 30 (12) ◽

pp. 1338-1340 ◽

Cited By ~ 19

Author(s):

L. Donetti ◽

F. Gamiz ◽

N. Rodriguez ◽

A. Godoy

Keyword(s):

Acoustic Phonon ◽

Hole Mobility ◽

Double Gate ◽

Phonon Confinement ◽

Soi Devices

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