Preparation of 200 mm silicon substrates with metal ground-plane for double-gate SOI devices

2002 ◽  
Author(s):  
L.J. Huang ◽  
K. Chan ◽  
P.M. Solomon ◽  
E. Jones ◽  
C. D'Emic ◽  
...  
Keyword(s):  
Ground Plane ◽  
Silicon Substrates ◽  
Double Gate ◽  
Soi Devices

Realization of Tunable Varactors Using Bi1.5Zn1.0Nb1.5O7 Thin Films

2009 ◽  
Vol 421-422 ◽  
pp. 153-156
Author(s):  
K. Sudheendran ◽  
K.C. James Raju
Keyword(s):  
Thin Films ◽  
Ground Plane ◽  
Silicon Substrates ◽  
Low Frequencies ◽  
Microwave Frequencies ◽  
Inner Radius ◽  
Voltage Dependent ◽  
Dc Bias ◽  
Fabrication And Characterization

Cubic pyrochlore bismuth zinc niobate thin films are known to exhibit voltage dependent dielectric properties. In this paper, we are demonstrating the fabrication and characterization of interdigital (IDC) and circular patch (CPC) capacitors using the pulsed laser deposited Bi1.5Zn1.0Nb1.5O7 (BZN) thin films on sapphire and platinised silicon substrates respectively. The IDCs fabricated are having 12 fingers of width 12 m each and separated by a gap of 8 m. The CPC are having circular patches with inner radius of 100 m and concentric ground plane with a radius of 300m. The electrical properties of these capacitors were characterized both at low frequencies and at microwave frequencies. The CPC varactors were having a tunability of 25% at 15 Volts. The calculated capacitance of the IDC varactor at 5.3 GHz with 0 V dc bias was 1.1 pF, which has got changed to 0.99 pF by the application of 30 Volts exhibiting a tunability of 10%.

MONTE-CARLO SIMULATION OF ULTRA-THIN FILM SILICON-ON-INSULATOR MOSFETs

2013 ◽  
Vol 22 (01) ◽  
pp. 1350001
Author(s):  
FRANCISCO GÁMIZ ◽  
CARLOS SAMPEDRO ◽  
LUCA DONETTI ◽  
ANDRES GODOY
Keyword(s):  
Monte Carlo ◽  
Ground Plane ◽  
Silicon On Insulator ◽  
Slab Thickness ◽  
Short Channel ◽  
Fully Depleted ◽  
Ensemble Monte Carlo ◽  
Soi Devices ◽  
Monte Carlo Simulator ◽  
The Impact

State-of-the-Art devices are approaching to the performance limit of traditional MOSFET as the critical dimensions are shrunk. Ultrathin fully depleted Silicon-on-Insulator transistors and multi-gate devices based on SOI technology are the best candidates to become a standard solution to overcome the problems arising from such aggressive scaling. Moreover, the flexibility of SOI wafers and processes allows the use of different channel materials, substrate orientations and layer thicknesses to enhance the performance of CMOS circuits. From the point of view of simulation, these devices pose a significant challenge. Simulations tools have to include quantum effects in the whole structure to correctly describe the behavior of these devices. The Multi-Subband Monte Carlo (MSB-MC) approach constitutes today's most accurate method for the study of nanodevices with important applications to SOI devices. After reviewing the main basis of MSB-MC method, we have applied it to answer important questions which remain open regarding ultimate SOI devices. In the first part of the chapter we present a thorough study of the impact of different Buried OXide (BOX) configurations on the scaling of extremely thin fully depleted SOI devices using a Multi-Subband Ensemble Monte Carlo simulator (MS-EMC). Standard thick BOX, ultra thin BOX (UTBOX) and UTBOX with ground plane (UTBOX+GP) solutions have been considered in order to check their influence on short channel effects (SCEs). The simulations show that the main limiting factor for downscaling is the DIBL and the UTBOX+GP configuration is the only valid one to downscale SGSOI transistors beyond 20 nm channel length keeping the silicon slab thickness above the theoretical limit of 5 nm, where thickness variability and mobility reduction would play an important role. In the second part, we have used the multisubband Ensemble Monte Carlo simulator to study the electron transport in ultrashort DGSOI devices with different confinement and transport directions. Our simulation results show that transport effective mass, and subband redistribution are the main factors that affect drift and scattering processes and, therefore, the general performance of DGSOI devices when orientation is changed

UTBB SOI MOSFETs analog figures of merit: Effects of ground plane and asymmetric double-gate regime

2013 ◽  
Vol 90 ◽  
pp. 56-64 ◽  
Author(s):  
M.K. Md Arshad ◽  
S. Makovejev ◽  
S. Olsen ◽  
F. Andrieu ◽  
J.-P. Raskin ◽  
...  
Keyword(s):  
Ground Plane ◽  
Double Gate ◽  
Figures Of Merit
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