Electrical characterization of atomic-layer-deposited hafnium silicate for alternative gate dielectric application

2005 ◽  
Author(s):  
S. Duenas ◽  
H. Castan ◽  
H. Garcia ◽  
J. Barbolla ◽  
K. Kukli ◽  
...  
Keyword(s):  
Gate Dielectric ◽  
Electrical Characterization ◽  
Atomic Layer ◽  
Hafnium Silicate

An Advanced High-k Transistor Utilizing Metal-Organic Precursors in an ALD Deposition of Hafnium Oxide and Hafnium Silicate with Ozone as Oxidizer

2004 ◽  
Vol 811 ◽  
Author(s):  
J. Gutt ◽  
G.A. Brown ◽  
Yoshi Senzaki ◽  
Seung Park
Keyword(s):  
Hafnium Oxide ◽  
High Performance ◽  
Gate Dielectric ◽  
Electrical Characterization ◽  
Atomic Layer ◽  
Oxide Thickness ◽  
Cmos Technology ◽  
Hafnium Silicate ◽  
High K ◽  
Metal Organic

AbstractThe International Technology Roadmap for Semiconductors (ITRS) has projected that continued scaling of planar CMOS technology to the 65nm node and beyond will require development of high-k films for transistor gate dielectric applications to allow further scaling of overall device sizes according to Moore's Law [1]. Researchers have recently been studying hafnium-based high-k dielectrics as an alternative to SiO2 [2]. The method of deposition of these films has been found to impact the applicability of the films for both low standby power and high performance applications [3]. Atomic Layer Deposition (ALD) has been among the more widely studied deposition techniques for these films, but previous work has emphasized ALD utilizing inorganic precursors [4]. In this paper, we shall describe a process in which hafnium oxide and hafnium silicate films were deposited from alternating pulses of volatile metal-organic Hf/Si liquid precursors and ozone on 200mm diameter Si substrates using a single wafer ALD system. Electrical characterization of the films is presented, including equivalent oxide thickness (EOT), gate leakage, and electron mobility data, showing an achievement of EOT's ranging from 1.19 to 1.69 nm with high field mobilities from 74% to more than 90% of that of SiO2 (2.1 nm film), and Jg in the range of 80mA to 3 A/cm2.

Electrical Characterization of Epitaxial Graphene Field-Effect Transistors with High-k Al2O3 Gate Dielectric Fabricated on SiC Substrates

2015 ◽  
Vol 821-823 ◽  
pp. 937-940 ◽  
Author(s):  
Toby Hopf ◽  
Konstantin Vassilevski ◽  
Enrique Escobedo-Cousin ◽  
Peter King ◽  
Nicholas G. Wright ◽  
...  
Keyword(s):  
Field Effect ◽  
Gate Dielectric ◽  
Field Effect Transistors ◽  
Electrical Characterization ◽  
Atomic Layer ◽  
Epitaxial Graphene ◽  
Vacuum Sublimation ◽  
Layer Deposition ◽  
High K

Top-gated field-effect transistors have been created from bilayer epitaxial graphene samples that were grown on SiC substrates by a vacuum sublimation approach. A high-quality dielectric layer of Al2O3was grown by atomic layer deposition to function as the gate oxide, with an e-beam evaporated seed layer utilized to promote uniform growth of Al2O3over the graphene. Electrical characterization has been performed on these devices, and temperature-dependent measurements yielded a rise in the maximum transconductance and a significant shifting of the Dirac point as the operating temperature of the transistors was increased.

scholarly journals Electrical Characterization of Postmetal Annealed Ultrathin TiN Gate Electrodes in Si MOS Capacitors

2016 ◽  
Vol 2016 ◽  
pp. 1-4 ◽  
Author(s):  
Z. N. Khan ◽  
S. Ahmed ◽  
M. Ali
Keyword(s):  
Electrical Characterization ◽  
Atomic Layer ◽  
Device Fabrication ◽  
Process Window ◽  
Gate Stacks ◽  
Mos Capacitors ◽  
Hafnium Silicate ◽  
Gate Electrodes ◽  
Layer Deposition ◽  
Tin Metal

Focusing on sub-10 nm Silicon CMOS device fabrication technology, we have incorporated ultrathin TiN metal gate electrode in Hafnium Silicate (HfSiO) based metal-oxide capacitors (MOSCAP) with carefully chosen Atomic Layer Deposition (ALD) process parameters. Gate element of the device has undergone a detailed postmetal annealed sequence ranging from 100°C to 1000°C. The applicability of ultrathin TiN on gate electrodes is established through current density versus voltage (J-V), resistance versus temperature (R-T), and permittivity versus temperature analysis. A higher process window starting from 600°C was intentionally chosen to understand the energy efficient behavior expected from ultrathin gate metallization and its unique physical state with shrinking thickness. The device characteristics in form of effective electronic mobility as a function of inverse charge density were also found better than those conventional gate stacks used for EOT scaling.

Optical and electrical characterization of atomic layer deposited (ALD) HfO2/p-GaAs MOS capacitors

2012 ◽  
Author(s):  
Anindita Das ◽  
Sanatan Chattopadhyay ◽  
Goutam K. Dalapati ◽  
Dongzhi Chi ◽  
M. K. Kumar
Keyword(s):  
Electrical Characterization ◽  
Atomic Layer ◽  
Mos Capacitors
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