MAGE: Adaptive Granularity and ECC for resilient and power efficient memory systems

2012 ◽  
Author(s):  
Sheng Li ◽  
Doe Hyun Yoon ◽  
Ke Chen ◽  
Jishen Zhao ◽  
Jung Ho Ahn ◽  
...  
Keyword(s):  
Memory Systems ◽  
Power Efficient ◽  
Efficient Memory

scholarly journals Study on the Implementation of a Simple and Effective Memory System for an AI Chip

Electronics ◽  
2021 ◽  
Vol 10 (12) ◽  
pp. 1399
Author(s):  
Taepyeong Kim ◽  
Sangun Park ◽  
Yongbeom Cho
Keyword(s):  
High Speed ◽  
Memory Systems ◽  
Memory System ◽  
External Memory ◽  
Essential Factor ◽  
Wide Bandwidth ◽  
Reading And Writing ◽  
Data Skew ◽  
Lower Performance ◽  
Efficient Memory

In this study, a simple and effective memory system required for the implementation of an AI chip is proposed. To implement an AI chip, the use of internal or external memory is an essential factor, because the reading and writing of data in memory occurs a lot. Those memory systems that are currently used are large in design size and complex to implement in order to handle a high speed and a wide bandwidth. Therefore, depending on the AI application, there are cases where the circuit size of the memory system is larger than that of the AI core. In this study, SDRAM, which has a lower performance than the currently used memory system but does not have a problem in operating AI, was used and all circuits were implemented digitally for simple and efficient implementation. In particular, a delay controller was designed to reduce the error due to data skew inside the memory bus to ensure stability in reading and writing data. First of all, it verified the memory system based on the You Only Look Once (YOLO) algorithm in FPGA to confirm that the memory system proposed in AI works efficiently. Based on the proven memory system, we implemented a chip using Samsung Electronics’ 65 nm process and tested it. As a result, we designed a simple and efficient memory system for AI chip implementation and verified it with hardware.

A Fast and Power-Efficient Memory-Centric Architecture for Affine Computation

2016 ◽  
Vol 63 (7) ◽  
pp. 668-672
Author(s):  
Shouyi Yin ◽  
Peng Ouyang ◽  
Leibo Liu ◽  
Shaojun Wei
Keyword(s):  
Power Efficient ◽  
Efficient Memory

Power-efficient Memory and Cache

2010 ◽  
pp. 89-138
Author(s):  
Preeti Ranjan Panda ◽  
Aviral Shrivastava ◽  
B. V. N. Silpa ◽  
Krishnaiah Gummidipudi
Keyword(s):  
Power Efficient ◽  
Efficient Memory

Efficient Runahead Execution: Power-Efficient Memory Latency Tolerance

IEEE Micro ◽  
2006 ◽  
Vol 26 (1) ◽  
pp. 10-20 ◽  
Author(s):  
O. Mutlu ◽  
Hyesoon Kim ◽  
Y.N. Patt
Keyword(s):  
Memory Latency ◽  
Power Efficient ◽  
Latency Tolerance ◽  
Efficient Memory ◽  
Runahead Execution

Compiler support for scalable and efficient memory systems

2001 ◽  
Vol 50 (11) ◽  
pp. 1234-1247 ◽  
Author(s):  
R. Barua ◽  
W. Lee ◽  
S. Arnarasinghe ◽  
A. Agarwal
Keyword(s):  
Memory Systems ◽  
Compiler Support ◽  
Efficient Memory

scholarly journals Efficient Memory Management for NVM-Based Hybrid Memory Systems

2016 ◽  
Vol 9 (1) ◽  
pp. 445-458 ◽  
Author(s):  
Zhangling Wu ◽  
Peiquan Jin ◽  
Chengcheng Yang ◽  
Lihua Yue
Keyword(s):  
Memory Management ◽  
Memory Systems ◽  
Hybrid Memory ◽  
Efficient Memory
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