Efficient Runahead Execution: Power-Efficient Memory Latency Tolerance

IEEE Micro ◽  
2006 ◽  
Vol 26 (1) ◽  
pp. 10-20 ◽  
Author(s):  
O. Mutlu ◽  
Hyesoon Kim ◽  
Y.N. Patt
Keyword(s):  
Memory Latency ◽  
Power Efficient ◽  
Latency Tolerance ◽  
Efficient Memory ◽  
Runahead Execution

A Fast and Power-Efficient Memory-Centric Architecture for Affine Computation

2016 ◽  
Vol 63 (7) ◽  
pp. 668-672
Author(s):  
Shouyi Yin ◽  
Peng Ouyang ◽  
Leibo Liu ◽  
Shaojun Wei
Keyword(s):  
Power Efficient ◽  
Efficient Memory

Power-efficient Memory and Cache

2010 ◽  
pp. 89-138
Author(s):  
Preeti Ranjan Panda ◽  
Aviral Shrivastava ◽  
B. V. N. Silpa ◽  
Krishnaiah Gummidipudi
Keyword(s):  
Power Efficient ◽  
Efficient Memory

scholarly journals Design Example of Useful Memory Latency for Developing a Hazard Preventive Pipeline High-Performance Embedded-Microprocessor

VLSI Design ◽  
2013 ◽  
Vol 2013 ◽  
pp. 1-10 ◽  
Author(s):  
Ching-Hwa Cheng
Keyword(s):  
Structural Control ◽  
High Performance ◽  
Architectural Design ◽  
Memory Hierarchy ◽  
Design Stage ◽  
Memory Latency ◽  
Hazard Detection ◽  
Embedded Microprocessor ◽  
Complex Relationships ◽  
Efficient Memory

The existence of structural, control, and data hazards presents a major challenge in designing an advanced pipeline/superscalar microprocessor. An efficient memory hierarchy cache-RAM-Disk design greatly enhances the microprocessor's performance. However, there are complex relationships among the memory hierarchy and the functional units in the microprocessor. Most past architectural design simulations focus on the instruction hazard detection/prevention scheme from the viewpoint of function units. This paper emphasizes that additional inboard memory can be well utilized to handle the hazardous conditions. When the instruction meets hazardous issues, the memory latency can be utilized to prevent performance degradation due to the hazard prevention mechanism. By using the proposed technique, a better architectural design can be rapidly validated by an FPGA at the start of the design stage. In this paper, the simulation results prove that our proposed methodology has a better performance and less power consumption compared to the conventional hazard prevention technique.

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