Design of Power-efficient Memory-based FFT Processor with New Memory Addressing Scheme

2006 ◽  
Author(s):  
Seungbeom Lee ◽  
Hyoungsoon Kim ◽  
Sin-chong Park
Keyword(s):  
Power Efficient ◽  
Fft Processor ◽  
Efficient Memory

A Fast and Power-Efficient Memory-Centric Architecture for Affine Computation

2016 ◽  
Vol 63 (7) ◽  
pp. 668-672
Author(s):  
Shouyi Yin ◽  
Peng Ouyang ◽  
Leibo Liu ◽  
Shaojun Wei
Keyword(s):  
Power Efficient ◽  
Efficient Memory

Power-efficient Memory and Cache

2010 ◽  
pp. 89-138
Author(s):  
Preeti Ranjan Panda ◽  
Aviral Shrivastava ◽  
B. V. N. Silpa ◽  
Krishnaiah Gummidipudi
Keyword(s):  
Power Efficient ◽  
Efficient Memory

Efficient Runahead Execution: Power-Efficient Memory Latency Tolerance

IEEE Micro ◽  
2006 ◽  
Vol 26 (1) ◽  
pp. 10-20 ◽  
Author(s):  
O. Mutlu ◽  
Hyesoon Kim ◽  
Y.N. Patt
Keyword(s):  
Memory Latency ◽  
Power Efficient ◽  
Latency Tolerance ◽  
Efficient Memory ◽  
Runahead Execution

scholarly journals Double Precision Floating Point Fft Processor using Vedic Mathematics

2019 ◽  
Vol 8 (4) ◽  
pp. 8533-8538
Keyword(s):  
Fourier Transform ◽  
Fast Fourier Transform ◽  
Floating Point ◽  
Double Precision ◽  
Power Efficient ◽  
Vedic Mathematics ◽  
Communication Signal ◽  
Fft Processor ◽  
Complex Multiplications ◽  
Point Fast Fourier Transform

There should be rapid, efficient and simple process for every scenario now a day. To compute the N point DFT, Fast Fourier Transform (FFT) is a productive algorithm. It has great applications in communication, signal and image processing and instrumentation. In the implementation of FFT one of the challenges is the complex multiplications, so to make this process rapid and simple it’s necessary for a multiplier to be fast and power efficient. To tackle this problem Karatsuba sutra and Nikhilam sutra are an efficient method of multiplication in Vedic Mathematics. This paper will present a design methodology of Double Precision Floating Point Fast Fourier Transform (FFT) Processor.The execution time and complexity can be reduced by the algorithm which is there in Vedic.The main aim is to make FFT Processor process rapid and simple by designing a multiplier which is fast and power efficient by using double precision floating point and Vedic Mathematics concepts.

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