ECC Parity: A Technique for Efficient Memory Error Resilience for Multi-Channel Memory Systems

2014 ◽  
Author(s):  
Xun Jian ◽  
Rakesh Kumar
Keyword(s):  
Error Resilience ◽  
Memory Systems ◽  
Memory Error ◽  
Channel Memory ◽  
Efficient Memory

scholarly journals Study on the Implementation of a Simple and Effective Memory System for an AI Chip

Electronics ◽  
2021 ◽  
Vol 10 (12) ◽  
pp. 1399
Author(s):  
Taepyeong Kim ◽  
Sangun Park ◽  
Yongbeom Cho
Keyword(s):  
High Speed ◽  
Memory Systems ◽  
Memory System ◽  
External Memory ◽  
Essential Factor ◽  
Wide Bandwidth ◽  
Reading And Writing ◽  
Data Skew ◽  
Lower Performance ◽  
Efficient Memory

In this study, a simple and effective memory system required for the implementation of an AI chip is proposed. To implement an AI chip, the use of internal or external memory is an essential factor, because the reading and writing of data in memory occurs a lot. Those memory systems that are currently used are large in design size and complex to implement in order to handle a high speed and a wide bandwidth. Therefore, depending on the AI application, there are cases where the circuit size of the memory system is larger than that of the AI core. In this study, SDRAM, which has a lower performance than the currently used memory system but does not have a problem in operating AI, was used and all circuits were implemented digitally for simple and efficient implementation. In particular, a delay controller was designed to reduce the error due to data skew inside the memory bus to ensure stability in reading and writing data. First of all, it verified the memory system based on the You Only Look Once (YOLO) algorithm in FPGA to confirm that the memory system proposed in AI works efficiently. Based on the proven memory system, we implemented a chip using Samsung Electronics’ 65 nm process and tested it. As a result, we designed a simple and efficient memory system for AI chip implementation and verified it with hardware.

Compiler support for scalable and efficient memory systems

2001 ◽  
Vol 50 (11) ◽  
pp. 1234-1247 ◽  
Author(s):  
R. Barua ◽  
W. Lee ◽  
S. Arnarasinghe ◽  
A. Agarwal
Keyword(s):  
Memory Systems ◽  
Compiler Support ◽  
Efficient Memory

scholarly journals Efficient Memory Management for NVM-Based Hybrid Memory Systems

2016 ◽  
Vol 9 (1) ◽  
pp. 445-458 ◽  
Author(s):  
Zhangling Wu ◽  
Peiquan Jin ◽  
Chengcheng Yang ◽  
Lihua Yue
Keyword(s):  
Memory Management ◽  
Memory Systems ◽  
Hybrid Memory ◽  
Efficient Memory

scholarly journals Complex synapses as efficient memory systems

2015 ◽  
Vol 16 (S1) ◽  
Author(s):  
Marcus K Benna ◽  
Stefano Fusi
Keyword(s):  
Memory Systems ◽  
Efficient Memory

EXPLOITING TEMPORAL LOCALITY FOR ENERGY EFFICIENT MEMORY MANAGEMENT

2008 ◽  
Vol 17 (05) ◽  
pp. 929-941 ◽  
Author(s):  
EUISEONG SEO ◽  
SEUNGRYOUL MAENG ◽  
DONGHYOUK LIM ◽  
JOONWON LEE
Keyword(s):  
Energy Efficient ◽  
Memory Management ◽  
Memory Systems ◽  
Major Power ◽  
Additional Energy ◽  
State Management ◽  
Research Activities ◽  
Management Scheme ◽  
Temporal Locality ◽  
Efficient Memory

Memory is becoming one of the major power consumers in computing systems. Therefore, energy efficient memory management is essential. Modern memory systems employ sleep states for energy saving. To utilize this feature, existing research activities have concentrated on increasing spatial locality to deactivate as many blocks as possible. However, they did not count the unexpected activation of memory blocks due to cache eviction of deactivated tasks. In this paper, we suggest a software-based power state management scheme for memory, which exploits temporal locality to relieve the energy loss from the unexpected activation of memory blocks from cache eviction. The suggested scheme SW-NAP makes a memory block remain deactivated during a certain tick, which has no cache miss over the block. The evaluation shows that SW-NAP is 50% better than PAVM, which is an existing software scheme, and worse than PMU, which is another approach based on the specialized hardware by 20%. We also suggest task scheduling policies that increase the effectiveness of SW-NAP and they saved up to 7% additional energy.

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